System Port C Pin Multiplexing Control Register: Low (Sim_Muxptcl); System Clock Gating Control 1 Register (Sim_Scgc1) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
9.8.11 System Port C Pin Multiplexing Control Register: Low
(SIM_MUXPTCL)
Many of the I/O pins are shared with on-chip peripheral functions. This register selects
the multiplexing pin functions from ALT0 to ALT3. Default is ALT0 function, When the
Pin Muxing mode is configured for analog pins, all the digital functions on that pin are
disabled, including the pullup/output/input.
The shared analog pin functions can work together if they're enabled separately because
they're directly connected to internal analog modules separately. They still work even
when pin Muxing mode is configured for digital pins.
Address: 1800h base + Ah offset = 180Ah
Bit 7
Read
Write
Reset 0
Field
7–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
MUXPTC0 Pin Mux Control
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.

9.8.12 System Clock Gating Control 1 Register (SIM_SCGC1)

This register contains control bits to enable or disable the bus clock to the PMC, DBG,
NVM, IPC and CRC modules. Gating off the clocks to unused peripherals is used to
reduce the MCU's run and wait currents.
User software must disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
116
6 5
0
0 0
SIM_MUXPTCL field descriptions
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0 0
Description
2 1
MUXPTC0
0 0
NXP Semiconductors
0
0