NXP Semiconductors MC9S08SU16 Reference Manual page 147

Source Form Operation
CMP oprx8,SP
COM opr8a
COMA
One's Complement
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
CPHX opr16a
CPHX #opr16i
CPHX opr8a Compare Index
Register (H:X) with
Memory
CPHX oprx8,SP
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X Compare X (Index
Register Low) with
Memory
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
DAA Decimal Adjust
Accumulator After
ADD or ADC of BCD
Values
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
Decrement and
DBNZ oprx8,X,rel
Branch if Not Zero
DBNZ ,X,rel
DBNZ
oprx8,SP,rel
DEC opr8a
DECA
DECX
NXP Semiconductors
Table 10-3. Instruction Set Summary (continued)
Description
M ← (M) = 0xFF – (M)
A ← (A) = 0xFF – (A)
X ← (X) = 0xFF – (X)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
(H:X) – (M:M +
0x0001); (CCR
Updated But Operands
Not Changed)
(X) – (M); (CCR
Updated But Operands
Not Changed)
(A)
10
Decrement A, X, or M
Branch if (result) ≠ 0
Affects X, Not H
M ← (M) – 0x01
A ← (A) – 0x01
X ← (X) – 0x01
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 10 Central processor unit
Effect on CCR
Address
V H I N Z C
Mode
– – SP1
↕ ↕ ↕ ↕
0 – – 1 DIR
↕ ↕
0 – – 1 INH
↕ ↕
0 – – 1 INH
↕ ↕
0 – – 1 IX1
↕ ↕
0 – – 1 IX
↕ ↕
0 – – 1 SP1
↕ ↕
– – EXT
↕ ↕ ↕ ↕
– – IMM
↕ ↕ ↕ ↕
– – DIR
↕ ↕ ↕ ↕
– – SP1
↕ ↕ ↕ ↕
− − IMM
↕ ↕ ↕ ↕
− − DIR
↕ ↕ ↕ ↕
− − EXT
↕ ↕ ↕ ↕
− − IX2
↕ ↕ ↕ ↕
− − IX1
↕ ↕ ↕ ↕
− − IX
↕ ↕ ↕ ↕
− − SP2
↕ ↕ ↕ ↕
− − SP1
↕ ↕ ↕ ↕
U − − INH
↕ ↕ ↕
− − − − − − DIR
− − − − − − INH
− − − − − − INH
− − − − − − IX1
− − − − − − IX
− − − − − − SP1
− − − DIR
↕ ↕ ↕
− − − INH
↕ ↕ ↕
− − − INH
↕ ↕ ↕
9EE1 ff 4
33 dd 5
43 1
53 1
63 ff 5
73 4
9E63 ff 6
3E hh ll 6
65 jj kk 3
75 dd 5
9EF3 ff 6
A3 ii 2
B3 dd 3
C3 hh ll 4
D3 ee ff 4
E3 ff 3
F3 3
9ED3 ee ff 5
9EE3 ff 4
72 1
3B dd rr 7
4B rr 4
5B rr 4
6B ff rr 7
7B rr 6
9E6B ff rr 8
3A dd 5
4A 1
5A 1
147