Mtim16 Counter Register High (Mtim_Cnth) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
5–4 Clock source select
CLKS
These two read/write bits select one of four different clock sources as the input to the MTIM16 prescaler.
Changing the clock source while the counter is active does not clear the counter. The count continues with
the new clock source. Reset clears CLKS to 00.
00 Encoding 0. Bus clock (BUSCLK)
01 Encoding 1. Fixed-frequency clock (XCLK)
10 Encoding 3. External source (TCLK pin), falling edge
11 Encoding 4. External source (TCLK pin), rising edge
PS Clock source prescaler
These four read/write bits select one of nine outputs from the 8-bit prescaler. Changing the prescaler value
while the counter is active does not clear the counter. The count continues with the new prescaler value.
Reset clears PS to 0000.
0000 Encoding 0. MTIM16 clock source / 1
0001 Encoding 1. MTIM16 clock source / 2
0010 Encoding 2. MTIM16 clock source / 4
0011 Encoding 3. MTIM16 clock source / 8
0100 Encoding 4. MTIM16 clock source / 16
0101 Encoding 5. MTIM16 clock source / 32
0110 Encoding 6. MTIM16 clock source / 64
0111 Encoding 7. MTIM16 clock source / 128
1xxx Encoding 8+. MTIM16 clock source / 256

13.5.3 MTIM16 counter register high (MTIM_CNTH)

This register is the read-only value of the high byte of the current MTIM16 16-bit
counter.
When either the CNTH or CNTL register is read, the content of the two registers is
latched into a buffer where they remain latched until the other register is read. This
allows the coherent 16-bit value to be read in both big-endian and little-endian compile
environments and ensures the 16-bit counter is unaffected by the read operation. The
coherency mechanism is automatically restarted by an MCU reset or by setting the TRST
bit of the SC register (whether BDM mode is active or not).
When BDM is active, the coherency mechanism is frozen such that the buffer latches
remain in the state they were in when BDM became active, even if one or both halves of
the counter register are read while BDM is active. This assures that if the user was in the
middle of reading a 16-bit register when BDM became active, the appropriate value from
the other half of the 16-bit value is read after returning to normal execution. The value
read from the CNTH and CNTL registers in BDM mode is the value of these registers
and not the value of their read buffer.
NXP Semiconductors
MTIM_CLK field descriptions (continued)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 13 Modulo Timer (MTIM)
Description
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