NXP Semiconductors LPC1102 Manuals

Manuals and User Guides for NXP Semiconductors LPC1102. We have 1 NXP Semiconductors LPC1102 manual available for free PDF download: User Manual

NXP Semiconductors LPC1102 User Manual (258 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 1 MB

Chapter 1: LPC1102 Introductory Information

3
Chapter 20 : LPC1102 Supplementary Information

3
Introduction

3
Features

3
Ordering Information

4
Chapter 2: LPC1102 Memory Mapping

7
How to Read this Chapter

7
Chapter 3: LPC1102 System Configuration

9
How to Read this Chapter

9
Introduction

9
Clocking and Power Control

9
Register Description

10
Deep-Sleep Mode Details

33
- IRC Oscillator
  33
- Start Logic
  33
- Wake-Up from Deep-Sleep Mode
  33
System PLL Functional Description

34
- Using the General Purpose Counter/Timers to Create a Self-Wake-Up Event
  34
- Lock Detector
  35
- Power-Down Control
  35
- Changing the Divider Values
  36
- Divider Ratio Programming
  36
- Feedback Divider
  36
- Frequency Selection
  36
- Normal Mode
  36
- Post Divider
  36
Flash Memory Access

37
- Power-Down Mode
  37
Chapter 4 : LPC1102 PMU (Power Management Unit)

39
- Power Control Register
  39
Chapter 5 : LPC1102 Power Profiles

40
Definitions

40
Clocking Routine

40
- Set_Pll
  40
- NXP B.V. 2010. All Rights Reserved
  40
  - Mode
    41
    
    System PLL Input Frequency and Expected System Clock
    41
    
    Code Examples
    42
    
    Invalid Frequency
    42
    
    Invalid Frequency Selection
    42
    
    System PLL Lock Timeout
    42
    
    Exact Solution Cannot be Found (PLL)
    43
    
    System Clock Less than or Equal to the Expected
    43
Chapter 6: LPC1102 Interrupt Controller

48
How to Read this Chapter

50
Introduction

50
Chapter 7: LPC1102 I/O Configuration

50
General Description

50
- Pin Function
  51
- Pin Mode
  51
Chapter 8: LPC1102 Pin Configuration

61
How to Read this Chapter

63
Chapter 9: LPC1102 General Purpose I/O (GPIO)

63
- Features
  63
Introduction

63
Register Description

63
Chapter 10 : LPC1102 Universal Asynchronous Transmitter (UART)

73
- UART Interrupt Identification Register (U0IIR - 0X4004 8008, Read Only)
  73
Chapter 11: LPC1102 SPI0 with SSP

90
How to Read this Chapter

90
Basic Configuration

90
Features

90
Pin Description

91
Register Description

91
Chapter 12: LPC1102 16-Bit Counter/Timers (CT16B0/1)

105
How to Read this Chapter

105
Basic Configuration

105
Features

105
Description

105
Pin Description

106
Register Description

106
- Tmr16B1Ir)
  107
Chapter 13 : LPC11102 32-Bit Counter/Timers (CT32B0/1)

108
Description

108
- Interrupt Register (TMR32B0IR and TMR32B1IR)
  108
  - Prescale Register
    109
    
    Timer Counter
    109
    
    External Match Register
    111
    
    PWM Control Register (TMR16B0PWMC and TMR16B1PWMC)
    113
    
    Rules for Single Edge Controlled PWM Outputs
    114
  - A/D Control Register
    141
Example Timer Operation

115
Chapter 14: LPC1102 Watchdog Timer (WDT)

131
- Timer Control Register (TMR16B0TCR and TMR16B1TCR)
  108
How to Read this Chapter

131
Features

131
Applications

131
Description

132
WDT Clocking

132
Register Description

132
Chapter 15: LPC1102 System Tick Timer

136
How to Read this Chapter

140
Basic Configuration

140
Chapter 16: LPC1102 Analog-To-Digital Converter (ADC)

140
- Bootloader
  147
ADC Clocking

141
Register Description

141
- A/D Global Data Register
  143
Chapter 17: LPC1102 Flash Memory Programming Firmware

147
How to Read this Chapter

147
- Memory Map after any Reset
  147
- Criterion for Valid User Code
  148
- Boot Process Flowchart
  149
- Code Read Protection (CRP)
  150
- Flash Content Protection Mechanism
  150
- Sector Numbers
  150
Features

147
General Description

147
UART Communication Protocol

152
UART ISP Commands

153
IAP Commands

161
- Cmd_Success
  164
- Copy RAM to Flash (IAP)
  164
- Count_Error
  164
- COUNT_ERROR (Byte Count Is Not 256 | 512 | 1024 | 4096) | SECTOR_NOT_PREPARED_FOR WRITE_OPERATION
  164
- Dst_Addr_Error
  164
- Dst_Addr_Not_Mapped
  164
- Invalid_Sector
  164
Return Mnemonic Code

164
- Src_Addr_Error
  164
- SRC_ADDR_ERROR (Address Not on Word Boundary) | DST_ADDR_ERROR (Address Not on Correct Boundary) | SRC_ADDR_NOT_MAPPED
  164
  - (Iap)
    165
  - Sector_Not_Blank
    165
  - Addr_Error
    166
  - Addr_Not_Mapped
    166
  - Compare_Error
    166
  - Reinvoke ISP (IAP)
    166
  - Readuid (IAP)
    167
Chapter 18: LPC1102 Serial Wire Debug (SWD)

173
How to Read this Chapter

173
Features

173
Introduction

173
Description

173
Chapter 19: Appendix Lpc1102 ARM Cortex-M0 Reference

175
Introduction

175
- Cortex-M0 Core Peripherals
  176
- Cortex-M0 Processor Features Summary
  176
- Integrated Configurable Debug
  176
- System-Level Interface
  176
- Core Registers
  177
About the Cortex-M0 Processor and Core Peripherals

175
Processor

177
- Processor Modes
  177
- Programmers Model
  177
- Stacks
  177
- General-Purpose Registers
  178
- Stack Pointer
  178
- Link Register
  179
- Program Counter
  179
- Program Status Register
  179
- CONTROL Register
  181
- Exception Mask Register
  181
- Data Types
  182
- Exceptions and Interrupts
  182
- The Cortex Microcontroller Software Interface Standard
  182
- Memory Model
  183
- Memory Regions, Types and Attributes
  184
- Behavior of Memory Accesses
  185
- Memory System Ordering of Memory Accesses
  185
- Software Ordering of Memory Accesses
  186
- Exception Model
  187
- Exception States
  187
- Exception Types
  188
- Exception Handlers
  189
- Vector Table
  189
- Exception Priorities
  190
- Exception Entry
  191
- Exception Entry and Return
  191
- Exception Return
  192
- Fault Handling
  193
- Lockup
  193
- Entering Sleep Mode
  194
- Power Management
  194
- Wait for Event
  194
- Wait for Interrupt
  194
Instruction Set

195
- Instruction Set Summary
  195
- Power Management Programming Hints
  195
- Sleep-On-Exit
  195
- Wake-Up from Sleep Mode
  195
- Wake-Up from WFE
  195
- Wake-Up from WFI or Sleep-On-Exit
  195
- Intrinsic Functions
  197
- About the Instruction Descriptions
  198
- Operands
  198
- Restrictions When Using PC or SP
  198
- NXP B.V. 2010. All Rights Reserved
  199
  - Asr
    199
  - Lsr
    199
  - Lsl
    200
  - Ror
    201
  - Address Alignment
    201
  - PC-Relative Expressions
    201
  - Conditional Execution
    202
  - The Condition Flags
    202
  - Condition Code Suffixes
    202
  - Memory Access Instructions
    203
  - Adr
    203
  - Syntax
    203
  - Operation
    204
  - Restrictions
    204
  - Condition Flags
    204
  - Examples
    204
  - LDR and STR, Immediate Offset
    204
  - Syntax
    204
  - Restrictions
    205
  - Condition Flags
    205
  - Examples
    205
  - LDR and STR, Register Offset
    205
  - Syntax
    205
  - Operation
    206
  - Restrictions
    206
  - Condition Flags
    206
  - Examples
    206
  - LDR, PC-Relative
    206
  - Syntax
    206
  - Examples
    207
  - LDM and STM
    207
  - Syntax
    207
  - Operation
    207
  - Restrictions
    207
  - Condition Flags
    208
  - Examples
    208
  - Incorrect Examples
    208
  - PUSH and POP
    208
  - Syntax
    208
  - Operation
    208
  - Restrictions
    208
  - Examples
    209
  - Syntax
    210
  - Operation
    210
  - Restrictions
    212
  - Examples
    212
  - Syntax
    212
  - Operation
    212
  - Restrictions
    213
  - Examples
    214
  - Syntax
    214
  - Restrictions
    214
  - Operation
    214
  - Muls
    215
  - Syntax
    215
  - Operation
    216
  - Restrictions
    216
  - Condition Flags
    216
  - Examples
    216
  - REV, REV16, and REVSH
    216
  - Syntax
    216
  - Restrictions
    217
  - Condition Flags
    217
  - Examples
    217
  - SXT and UXT
    217
  - Syntax
    217
  - Operation
    217
  - Examples
    218
  - Tst
    218
  - Syntax
    218
  - Operation
    218
  - Restrictions
    218
  - Syntax
    219
  - Operation
    219
  - Restrictions
    219
  - Condition Flags
    220
  - Examples
    220
  - Bkpt
    220
  - Syntax
    221
  - Operation
    221
  - Restrictions
    221
  - Examples
    221
  - Cps
    221
  - Restrictions
    222
  - Condition Flags
    222
  - Examples
    222
  - Dmb
    222
  - Syntax
    222
  - Operation
    222
  - Dsb
    222
  - Examples
    223
  - Isb
    223
  - Syntax
    223
  - Operation
    223
  - Restrictions
    223
  - Mrs
    223
  - Examples
    224
  - Msr
    224
  - Syntax
    224
  - Operation
    224
  - Restrictions
    224
  - Nop
    224
  - Examples
    225
  - Sev
    225
  - Syntax
    225
  - Operation
    225
  - Restrictions
    225
  - Condition Flags
    225
  - Svc
    225
  - Restrictions
    226
  - Examples
    226
  - Wfi
    226
  - Syntax
    226
  - Operation
    227
  - Restrictions
    227
  - Condition Flags
    227
  - Examples
    227
Peripherals

227
- Shift Operations
  199
- About the ARM Cortex-M0
  227
- Nested Vectored Interrupt Controller
  227
- Accessing the Cortex-M0 NVIC Registers Using CMSIS
  228
- Interrupt Set-Enable Register
  228
- Interrupt Clear-Enable Register
  229
- Interrupt Set-Pending Register
  229
- Interrupt Clear-Pending Register
  230
- Interrupt Priority Registers
  230
- Hardware and Software Control of Interrupts
  231
- Level-Sensitive and Pulse Interrupts
  231
- System Control Block
  232
- CPUID Register
  233
- Application Interrupt and Reset Control Register
  235
- System Control Register
  236
- Configuration and Control Register
  237
- System Handler Priority Registers
  237
- SCB Usage Hints and Tips
  238
- System Timer, Systick
  238
- Calculating the RELOAD Value
  239
- Systick Control and Status Register
  239
- Systick Current Value Register
  239
- Systick Reload Value Register
  239
Cortex-M0 Instruction Summary

240
- Systick Calibration Value Register
  240
- Systick Usage Hints and Tips
  240
- Disclaimers
  245
- Trademarks
  245
Tables

246
Figures

250

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NXP Semiconductors LPC1102 Manuals

NXP Semiconductors LPC1102 User Manual (258 pages)

Table of Contents

Chapter 1: LPC1102 Introductory Information

Chapter 20 : LPC1102 Supplementary Information

Introduction

Features

Ordering Information

Chapter 2: LPC1102 Memory Mapping

How to Read this Chapter

Chapter 3: LPC1102 System Configuration

How to Read this Chapter

Introduction

Clocking and Power Control

Register Description

Deep-Sleep Mode Details

System PLL Functional Description

Flash Memory Access

Chapter 4 : LPC1102 PMU (Power Management Unit)

Chapter 5 : LPC1102 Power Profiles

Definitions

Clocking Routine

Chapter 6: LPC1102 Interrupt Controller

How to Read this Chapter

Introduction

Chapter 7: LPC1102 I/O Configuration

General Description

Chapter 8: LPC1102 Pin Configuration

How to Read this Chapter

Chapter 9: LPC1102 General Purpose I/O (GPIO)

Introduction

Register Description

Chapter 10 : LPC1102 Universal Asynchronous Transmitter (UART)

Chapter 11: LPC1102 SPI0 with SSP

How to Read this Chapter

Basic Configuration

Features

Pin Description

Register Description

Chapter 12: LPC1102 16-Bit Counter/Timers (CT16B0/1)

How to Read this Chapter

Basic Configuration

Features

Description

Pin Description

Register Description

Chapter 13 : LPC11102 32-Bit Counter/Timers (CT32B0/1)

Description

Example Timer Operation

Chapter 14: LPC1102 Watchdog Timer (WDT)

How to Read this Chapter

Features

Applications

Description

WDT Clocking

Register Description

Chapter 15: LPC1102 System Tick Timer

How to Read this Chapter

Basic Configuration

Chapter 16: LPC1102 Analog-To-Digital Converter (ADC)

ADC Clocking

Register Description

Chapter 17: LPC1102 Flash Memory Programming Firmware

How to Read this Chapter

Features

General Description

UART Communication Protocol

UART ISP Commands

IAP Commands

Return Mnemonic Code

Chapter 18: LPC1102 Serial Wire Debug (SWD)

How to Read this Chapter

Features

Introduction

Description

Chapter 19: Appendix Lpc1102 ARM Cortex-M0 Reference

Introduction

About the Cortex-M0 Processor and Core Peripherals

Processor

Instruction Set