Pwtin[3:0] — Pulse Width Timer Capture Inputs - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions
Signal
PWTIN[3:0]
ALTCLK
20.3.2 PWTIN[3:0] — pulse width timer capture inputs
The input signals are pulse capture inputs which can come from internal or external. The
PWT input is selected by PINSEL[1:0] to be routed to the pulse width timer. If the input
comes from external and is selected as the PWT input, the input port is enabled for PWT
function by PINSEL[1:0] automatically. The minimum pulse width to be measured is 1
PWTCLK cycle, any pulse narrower than this value is ignored by PWT module. The
PWTCLK cycle time depends on the PWT clock source selection and pre-scaler rate
setting.
20.3.3 ALTCLK— alternative clock source for counter
The PWT has an alternative clock input ALTCLK which can be selected as the clock
source of the counter when the PCLKS bit is set. The ALTCLK input must be
synchronized by the bus clock. Variations in duty cycle and clock jitter must also be
accommodated so that the ALTCLK signal must not exceed one-fourth of the bus
frequency. The ALTCLK pin can be shared with a general-purpose port pin. See the Pins
and Connections chapter for the pin location and priority of this function.
20.4 Memory Map and Register Descriptions
Absolute
address
(hex)
30 Pulse Width Timer Control and Status Register (PWT0_CS)
31 Pulse Width Timer Control Register (PWT0_CR)
Pulse Width Timer Positive Pulse Width Register: High
32
(PWT0_PPH)
Pulse Width Timer Positive Pulse Width Register: Loq
33
(PWT0_PPL)
346
Table 20-2. PWT signal properties
Pullup
No
No
PWT memory map
Register name
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
Pulse inputs
Alternative clock source for
the counter
Width
Access
(in bits)
8 R/W
8 R/W
8 R
8 R
I/O
I
I
Section/
Reset value
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