Pulse Width Timer Positive Pulse Width Register: High (Pwtx_Pph) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
7 PWT Clock Source Selection
PCLKS
Controls the selection of clock source for the PWT counter.
0 BUS_CLK is selected as the clock source of PWT counter.
1 Alternative clock is selected as the clock source of PWT counter.
6–5 PWT Pulse Inputs Selection
PINSEL
Enables the corresponding PWT input port, if this PWT input comes from an external source.
00 PWTIN[0] is enabled.
01 PWTIN[1] is enabled.
10 PWTIN[2] enabled.
11 PWTIN[3] enabled.
4 PWTIN states Toggled from last state
TGL
This flag indicates if the selected PWTIN has toggled its state since last time this bit has cleared to 0.
0 The selected PWTIN hasn't changed its original states from last time.
1 The selected PWTIN has toggled its states.
3 PWTIN Level when Overflows
LVL
This Read Only bit signalizes the selected PWTIN states when the coutner overflows to read out.
PRE PWT Clock Prescaler (CLKPRE) Setting
Selects the value by which the clock is divided to clock the PWT counter.
000 Clock divided by 1.
001 Clock divided by 2.
010 Clock divided by 4.
011 Clock divided by 8.
100 Clock divided by 16.
101 Clock divided by 32.
110 Clock divided by 64.
111 Clock divided by 128.
20.4.3 Pulse Width Timer Positive Pulse Width Register: High
(PWTx_PPH)
Address: Base address + 2h offset
Bit 7
Read
Write
Reset 0
NXP Semiconductors
PWTx_CR field descriptions
6 5
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 20 Pules Width Timer (PWT)
Description
4 3
PPWH
0 0
2 1
0 0
0
0
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