Vrefh Low Voltage Warning (Lvw) Configuration Register (Pmc_Vrefhlvw); Status Register (Pmc_Stat) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
T5V Trim 5 V reference voltage for ADC
Auto-loaded from IFR.
After de-assert of system reset, a trim value is automatically loaded from the flash memory. The default is
3.8 V.
NOTE: Normal IPS writable only after PMC_CTRL[GWREN] is set.
14.7.9 VREFH Low Voltage Warning (LVW) Configuration Register
(PMC_VREFHLVW)
Address: 1850h base + 8h offset = 1858h
Bit 7
Read
Write
Reset 0
Field
7–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
LVWCFG[1:0] VREFH LVW reference voltage Configuration
These bits are used to configure the VREFH low voltage warning threshold value.
00 3.6 V LVW threshold.
01 3.7 V LVW threshold.
10 4.1 V LVW threshold.
11 4.4 V LVW threshold.

14.7.10 Status Register (PMC_STAT)

Address: 1850h base + 9h offset = 1859h
Bit 7
Read
Write
Reset 0
228
PMC_VREFHCFG field descriptions
6 5
0
0 0
PMC_VREFHLVW field descriptions
6 5
0
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
0 0
Description
4 3
HBGRDY
0 0
2 1
LVWCFG[1:0]
0 1
2 1
0 VREFRDY
1 0
NXP Semiconductors
0
0
0
0