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Background debug controller (BDC)
• BDC clock runs in stop mode, if BDC enabled
• Watchdog disabled by default while in active background mode. It can also be
enabled by proper configuration
Features of the ICE system include:
• Two trigger comparators: Two address + read/write (R/W) or one full address + data
+ R/W
• Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
• Change-of-flow addresses or
• Event-only data
• Two types of breakpoints:
• Tag breakpoints for instruction opcodes
• Force breakpoints for any address access
• Nine trigger modes:
• Basic: A-only, A OR B
• Sequence: A then B
• Full: A AND B data, A AND NOT B data
• Event (store data): Event-only B, A then event-only B
• Range: Inside range (A ≤ address ≤ B), outside range (address < A or address >
B)
27.2 Background debug controller (BDC)
All MCUs in the HCS08 Family contain a single-wire background debug interface that
supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-
intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system
does not interfere with normal application resources. It does not use any user memory or
locations in the memory map and does not share any on-chip peripherals.
BDC commands are divided into two groups:
• Active background mode commands require that the target MCU is in active
background mode (the user program is not running). Active background mode
commands allow the CPU registers to be read or written, and allow the user to trace
one user instruction at a time, or GO to the user program from active background
mode.
• Non-intrusive commands can be executed at any time even while the user's program
is running. Non-intrusive commands allow a user to read or write MCU memory
locations or access status and control registers within the background debug
controller.
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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