NXP Semiconductors MC9S08SU16 Reference Manual page 140

Operation modes
1. The RAM, flash, and EEPROM arrays are considered secure memory. All registers
in Direct Page or High Page are considered non-secure memory.
2. Read data is tagged as either secure or non-secure during a program read, depending
on whether the read is from secure or non-secure memory.
3. A data read of secure memory returns a value of $00 when the current instruction is
tagged as non-secure or the access is a BDC access.
4. A data write to secure memory is blocked and data at the target address does not
change state when the current instruction is tagged as non-secure or the access is
through BDC.
5. A data write to secure memory is never blocked during the stacking cycles of
interrupt service routines.
6. Data accesses to either secure or non-secure memory are allowed when the current
instruction is tagged as secure.
7. BDC accesses to non-secure memory are allowed.
When the device is in the non-secure mode, secure memory is treated the same as non-
secure memory, and all accesses are allowed.
Table 10-2 details the security conditions for allowing or disabling a read access.
Ram, flash or
Security
EEPROM
enabled
access
0
1 0
1 1
1 1
1 1
1 1
1 1
140
Table 10-2. Security conditions for read access
Inputs conditions
Program or
vector read
x x
x
1
0
0
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Current CPU instruction
from secure memory
x
x
x
1
1
0
0
Read control
Current access Read access
is via BDC allowed
x 1
x 1
x 1
0 1
1 0
0 0
1 0
NXP Semiconductors