NXP Semiconductors MC9S08SU16 Reference Manual page 66

System clock distribution
The system clock is bus clock.
For this device, the master clock and system/bus clock are the
same clock.
The following figure shows a simplified clock connection diagram.
LP OC LK
20 kHz
LPO
ICSIRCLK
32 kHz
IRC
ICSFFCLK
ICSOUTCLK
HSCLK
DIV3
ICS
MSTRCLK
DIV1
ICSBDCCLK
CLKIN
CLKOUT
20 MHz after reset
ICSOUTCLK: ~
The clock system supplies:
• ICSOUTCLK — This up to 40 MHz clock source is used as the master clock and bus
clock and high speed clock that is the reference to CPU and all peripherals. Control
bits in the ICS control registers determine which of two clock sources is connected:
• 32 kHz Internal reference clock
• Frequency-locked loop (FLL) output
There are three clocks that are derived from this clock source:
• MSTRCLK — Master clock is the clock source for CPU and RAM and DBG
and system/ bus clock
66
MTIM
WDOG
1/2
BUSCLK
DIV2
CPU RAM
1
N
2
BUSREF
System Control
Figure 5-1. System clock distribution diagram
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NOTE
NOTE
TCLK
CLKIN
ADC0
ACMP FTM
ADC1
DBG BDC FLASH
PWT0
PDB GDU
PWM
PWT1
IPC I2C
SCI KBI
NXP Semiconductors
PMC
CRC