Table of Contents
Advertisement
Memory Map/Register Definitions
Field
000
Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not
recommended). If SE = 0, COUT = COUTA.
001
1 consecutive sample must agree (comparator output is simply sampled).
010
2 consecutive samples must agree.
011
3 consecutive samples must agree.
100
4 consecutive samples must agree.
101
5 consecutive samples must agree.
110
6 consecutive samples must agree.
111
7 consecutive samples must agree.
3–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Comparator hard block hysteresis control
HYSTCTR
Defines the programmable hysteresis level. The hysteresis values associated with each level is device-
specific. See the device's data sheet for the exact values.
0
Level 0
1
Level 1
18.10.2 CMP Control Register 1 (CMP_CR1)
Address: 68h base + 1h offset = 69h
Bit
7
Read
SE
Write
Reset
0
Field
7
Sample Enable
SE
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set
and WE is cleared. However, avoid writing ones to both bit locations because this "11" case is reserved
and may change in future implementations.
0
Sampling mode not selected.
1
Sampling mode selected.
6
Windowing Enable
WE
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set
and WE is cleared. However, avoid writing ones to both bit locations because this "11" case is reserved
and may change in future implementations.
0
Windowing mode not selected.
1
Windowing mode selected.
296
CMP_CR0 field descriptions (continued)
6
5
0
WE
PMODE
0
0
CMP_CR1 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
INV
COS
0
0
Description
2
1
OPE
EN
0
0
NXP Semiconductors
0
0
Advertisement
Table of Contents
