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Field
FIFO is fulfilled. In continuous mode (ADCO = 1), ADC will start next conversion with the same channel
when COCO is set.
0
FIFO scan mode disabled.
1
FIFO scan mode enabled.
5
Compare function select OR/AND when the FIFO function is enabled (AFDEP > 0). When this field is
ACFSEL
cleared, ADC will OR all of compare triggers and set COCO after at least one of compare trigger occurs.
When this field is set, ADC will AND all of compare triggers and set COCO after all of compare triggers
occur.
0
OR all of compare trigger.
1
AND all of compare trigger.
4
Hardware Trigger Mask Enable
HTRGMASKE
This field enables hardware trigger mask when HTRGMASKSEL is low.
0
Hardware trigger mask disable.
1
Hardware trigger mask enable and hardware trigger cannot trigger ADC conversion..
3
Hardware Trigger Mask Mode Select
HTRGMASKSEL
This field selects hardware trigger mask mode.
0
Hardware trigger mask with HTRGMASKE.
1
Hardware trigger mask automatically when data fifo is not empty.
AFDEP
FIFO Depth enables the FIFO function and sets the depth of FIFO. When AFDEP is cleared, the FIFO is
disabled. When AFDEP is set to nonzero, the FIFO function is enabled and the depth is indicated by the
AFDEP bits. The ADCH in ADC_SC1 and ADC_RH:ADC_RL must be accessed by FIFO mode when
FIFO function is enabled. ADC starts conversion when the analog channel FIFO is upon the level
indicated by AFDEP bits. The COCO bit is set when the set of conversions are completed and the result
FIFO is upon the level indicated by AFDEP bits.
NOTE: The bus clock frequency must be at least double the ADC clock when FIFO mode is enabled. It
000
FIFO is disabled.
001
2-level FIFO is enabled.
010
3-level FIFO is enabled..
011
4-level FIFO is enabled.
100
5-level FIFO is enabled.
101
6-level FIFO is enabled.
110
7-level FIFO is enabled.
111
8-level FIFO is enabled.
17.4.5 Conversion Result High Register (ADCx_RH)
In 12-bit operation, ADC_RH contains the upper four bits of the result of a 12-bit
conversion.
NXP Semiconductors
ADCx_SC4 field descriptions (continued)
means, if ICS FBE mode is used, the ADC clock can not be ADACK.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 17 Analog-to-digital converter (ADC)
Description
267
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