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Chapter 27 Development support
27.3.5 Trigger modes
The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the
DBGT register selects one of nine trigger modes. When TRGSEL = 1 in the DBGT
register, the output of the comparator must propagate through an opcode tracking circuit
before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO
begins storing data when the qualified trigger is detected (begin trace), or the FIFO stores
data in a circular fashion from the time it is armed until the qualified trigger is detected
(end trigger).
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the
ARMF flag and clears the AF and BF flags and the CNT bits in DBGS. A begin-trace
debug run ends when the FIFO gets full. An end-trace run ends when the selected trigger
event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN
in DBGC.
In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses.
In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are
begin type traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary
to use R/W in comparisons because opcode tags would apply only to opcode fetches that
are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a
full mode trigger because the opcode value is normally known at a particular address.
The following trigger mode descriptions state only the primary comparator conditions
that lead to a trigger. Either comparator can usually be further qualified with R/W by
setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched
against R/W. The signal from the comparator with optional R/W qualification is used to
request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request
will be a tag request or a force request.
A-Only ̶ Trigger when the address matches the value in comparator A
A OR B ̶ Trigger when the address matches either the value in comparator A or the value
in comparator B
A Then B ̶ Trigger when the address matches the value in comparator B but only after
the address for another cycle matched the value in comparator A. There can be any
number of cycles after the A match and before the B match.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
541
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