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11.3.5.1 Writing the FCLKDIV register
Prior to issuing any flash program or erase command after a reset, the user is required to
write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. The
following table shows recommended values for FCLKDIV[FDIV] based on BUSCLK
frequency.
Table 11-2. FDIV values for various BUSCLK frequencies
BUSCLK frequency
1
MIN
1.0
1.6
2.6
3.6
4.6
5.6
6.6
7.6
8.6
9.6
10.6
11.6
12.6
13.6
14.6
15.6
16.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
1. BUSCLK is greater than this value.
2. BUSCLK is less than or equal to this value.
NXP Semiconductors
(MHz)
2
MAX
1.6
2.6
3.6
4.6
5.6
6.6
7.6
8.6
9.6
10.6
11.6
12.6
13.6
14.6
15.6
16.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 11 Flash Memory Module (FTMRH)
FDIV[5:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
159
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