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Initialization information
17.6.2.1 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single
hardware triggered 10-bit 4-level-FIFO conversion at low power with a long sample time
on input channels of 1, 3, 5, and 7. Here the internal ADCK clock is derived from the bus
clock divided by 1.
Example: 17.6.2.1.1 FIFO ADC initialization routine
void ADC_init(void)
{
/* The following code segment demonstrates how to initialize ADC by low-power mode, long
sample time, bus frequency, hardware triggered from AD1, AD3, AD5, and AD7 external pins
with 4-level FIFO enabled */
ADC_SC3 = ADC_SC3_ADLPC_MASK | ADC_SC3_ADLSMP_MASK | ADC_SC3_MODE1_MASK;
// setting hardware trigger
ADC_SC2 = ADC_SC2_ADTRG_MASK ;
//4-Level FIFO
ADC_SC4 = ADC_SC4_AFDEP1_MASK | ADC_SC4_AFDEP0_MASK;
// dummy the 1st channel
ADC_SC1 = ADC_SC1_ADCH0_MASK;
// dummy the 2nd channel
ADC_SC1 = ADC_SC1_ADCH1_MASK | ADC_SC1_ADCH0_MASK;
// dummy the 3rd channel
ADC_SC1 = ADC_SC1_ADCH2_MASK | ADC_SC1_ADCH0_MASK;
// dummy the 4th channel and ADC starts conversion
ADC_SC1 = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH2_MASK | ADC_SC1_ADCH1_MASK | ADC_SC1_ADCH0_MASK;
}
Example: 17.6.2.1.2 FIFO ADC interrupt service routine
unsigned short buffer[4];
interrupt VectorNumber_Vadc void ADC_isr(void)
{
/* The following code segment demonstrates read AD result FIFO */
// read conversion result of channel 1 and COCO bit is cleared
buffer[0] = ADC_R;
// read conversion result of channel 3
buffer[1] = ADC_R;
// read conversion result of channel 5
buffer[2] = ADC_R;
// read conversion result of channel 7
buffer[3] = ADC_R;
}
ADC_R is 16-bit ADC result register, combined from
ADC_RH and ADC_RL
282
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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