Debug Fifo Extended Information Register (Dbg_Fx) - NXP Semiconductors MC9S08SU16 Reference Manual

28.3.12 Debug FIFO Extended Information Register (DBG_FX)

All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + Bh offset = 18CBh
Bit 7
Read PPACC
Write
Reset
0
Field
7 PPAGE Access Indicator Bit
PPACC
This bit indicates whether the captured information in the current FIFO word is associated with an
extended access through the PPAGE mechanism or not. This is indicated by the internal signal
mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.
0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU address
with bit-16 = 0.
1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the three
most significant bits and CPU address[13:0] in the 14 least significant bits.
6–1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Extended Address Bit 16
Bit16
This bit is the most significant bit of the 17-bit core address.
28.3.13 Debug Control Register (DBG_C)
Address: 18C0h base + Ch offset = 18CCh
Bit 7
Read
DBGEN
Write
Reset
1
NXP Semiconductors
NOTE
6 5
0 0
DBG_FX field descriptions
6 5
ARM TAG BRKEN
1 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0
0 0
Description
4 3
0 0
Chapter 28 Debug module (DBG)
2 1
Bit16
0 0
2 1
0
LOOP1
0 0
0
0
0
0
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