NXP Semiconductors MC9S08PA4 Reference Manual
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NXP Semiconductors MC9S08PA4 Reference Manual

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MC9S08PA4 Reference Manual
Supports: MC9S08PA4
Document Number: MC9S08PA4RM
Rev. 5, 08/2017

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Summary of Contents for NXP Semiconductors MC9S08PA4

  • Page 1 MC9S08PA4 Reference Manual Supports: MC9S08PA4 Document Number: MC9S08PA4RM Rev. 5, 08/2017...
  • Page 2 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 3: Table Of Contents

    Chapter 3 Power management Introduction..................................37 Features................................... 37 3.2.1 Run mode................................. 37 3.2.2 Wait mode................................ 38 3.2.3 Stop3 mode..............................38 3.2.4 Active BDM enabled in stop3 mode........................38 3.2.5 LVD enabled in stop mode..........................39 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 4 Flash and EEPROM interrupts......................64 4.5.2.6 Protection............................65 4.5.2.7 Security............................68 4.5.2.8 Flash and EEPROM commands.......................70 4.5.2.9 Flash and EEPROM command summary..................72 Flash and EEPROM registers descriptions........................86 4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...................86 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 5 5.2.1.2 Edge and level sensitivity........................ 107 Interrupt pin request register............................107 5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC)................. 108 Interrupt priority control register............................ 109 5.4.1 IPC Status and Control Register (IPC_SC)......................110 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 6 System Device Identification Register: Low (SYS_SDIDL)................122 6.6.5 System Options Register 1 (SYS_SOPT1)...................... 122 6.6.6 System Options Register 2 (SYS_SOPT2)...................... 124 6.6.7 System Options Register 3 (SYS_SOPT3)...................... 125 6.6.8 Illegal Address Register: High (SYS_ILLAH)....................126 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 7 Port C Output Enable Register (PORT_PTCOE).................... 139 7.7.8 Port A Input Enable Register (PORT_PTAIE)....................140 7.7.9 Port B Input Enable Register (PORT_PTBIE)....................141 7.7.10 Port C Input Enable Register (PORT_PTCIE)....................142 7.7.11 Port Filter Register 0 (PORT_IOFLT0)......................143 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 8 8.2.3 FLL lock and clock monitor..........................161 8.2.3.1 FLL clock lock..........................161 8.2.3.2 External reference clock monitor..................... 161 Initialization / application information........................... 161 8.3.1 Initializing FEI mode............................162 8.3.2 Initializing FBI mode............................162 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 9 System Clock Gating Control 4 Register (SCG_C4)..................175 Chapter 9 Chip configurations Introduction..................................177 Core modules.................................. 177 9.2.1 Central processor unit (CPU)........................... 177 9.2.2 Debug module (DBG)............................177 System modules................................178 9.3.1 Watchdog (WDOG)............................178 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 10 ACMP in stop3 mode........................193 9.9.2.3 ACMP to FTM configuration information..................193 9.9.2.4 ACMP for SCI0 RXD filter......................193 9.10 Human-machine interfaces HMI.............................194 9.10.1 Keyboard interrupts (KBI)..........................194 Chapter 10 Central processor unit 10.1 Introduction..................................197 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 11 10.3.7.1 Direct to Direct..........................206 10.3.7.2 Immediate to Direct......................... 206 10.3.7.3 Indexed to Direct, Post Increment....................206 10.3.7.4 Direct to Indexed, Post-Increment....................207 10.4 Operation modes................................207 10.4.1 Stop mode................................ 207 10.4.2 Wait mode................................ 207 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 12 11.4.3 KBIx Edge Select Register (KBIx_ES)......................229 11.5 Functional Description..............................229 11.5.1 Edge-only sensitivity............................230 11.5.2 Edge and level sensitivity..........................230 11.5.3 KBI Pullup Resistor............................230 11.5.4 KBI initialization..............................230 Chapter 12 FlexTimer Module (FTM) MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 13 Clock Source..............................245 12.4.1.1 Counter Clock Source........................245 12.4.2 Prescaler................................246 12.4.3 Counter................................246 12.4.3.1 Up counting............................246 12.4.3.2 Up-down counting..........................247 12.4.3.3 Free running counter........................248 12.4.3.4 Counter reset............................ 248 12.4.4 Input capture mode............................248 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 14 RTC Modulo Register: Low (RTC_MODL)....................263 13.3.5 RTC Counter Register: High (RTC_CNTH)....................263 13.3.6 RTC Counter Register: Low (RTC_CNTL)....................264 13.4 Functional description..............................264 13.4.1 RTC operation example........................... 265 13.5 Initialization/application information..........................266 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 15 14.4.3.1 Data sampling technique........................286 14.4.3.2 Receiver wake-up operation......................287 14.4.4 Interrupts and status flags..........................288 14.4.5 Baud rate tolerance............................289 14.4.5.1 Slow data tolerance.......................... 289 14.4.5.2 Fast data tolerance..........................291 14.4.6 Additional SCI functions..........................292 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 16 Compare Value Low Register (ADC_CVL)....................305 15.3.9 Pin Control 1 Register (ADC_APCTL1)......................306 15.4 Functional description..............................307 15.4.1 Clock select and divide control........................307 15.4.2 Input select and pin control..........................308 15.4.3 Hardware trigger.............................. 308 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 17 15.6.1.2 Analog reference pins........................321 15.6.1.3 Analog input pins..........................322 15.6.2 Sources of error..............................323 15.6.2.1 Sampling error..........................323 15.6.2.2 Pin leakage error..........................323 15.6.2.3 Noise-induced errors........................323 15.6.2.4 Code width and quantization error....................324 15.6.2.5 Linearity errors..........................325 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 18 Block diagram..............................336 17.2 Memory map and register definition..........................337 17.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)................337 17.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)................339 17.2.3 Watchdog Counter Register: High (WDOG_CNTH)..................340 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 19 17.3.7.2 Entering user mode.......................... 350 Chapter 18 Development support 18.1 Introduction..................................351 18.1.1 Forcing active background..........................351 18.1.2 Features................................351 18.2 Background debug controller (BDC)..........................352 18.2.1 BKGD pin description............................. 353 18.2.2 Communication details............................ 354 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 20 Debug Comparator B High Register (DBG_CBH)..................376 19.3.4 Debug Comparator B Low Register (DBG_CBL)...................376 19.3.5 Debug Comparator C High Register (DBG_CCH)..................377 19.3.6 Debug Comparator C Low Register (DBG_CCL)...................378 19.3.7 Debug FIFO High Register (DBG_FH)......................378 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 21 19.4.4.3 Trigger modes..........................392 19.4.5 FIFO................................. 394 19.4.5.1 Storing data in FIFO........................395 19.4.5.2 Storing with begin-trigger........................ 395 19.4.5.3 Storing with end-trigger........................395 19.4.5.4 Reading data from FIFO........................395 19.4.6 Interrupt priority...............................396 19.5 Resets....................................397 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 22 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 23: Device Overview

    4,096 EEPROM size (bytes) RAM size (bytes) SOIC-20 TSSOP-16 DFN-8 Table 1-2. Feature availability Pin number 20-pin 16-pin 8-pin Bus frequency (MHz) WDOG XOSC SCI0 ACMP Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 24: Mcu Block Diagram

    FTM0 channels 2-ch 2-ch 2-ch FTM1 channels 2-ch 2-ch 1-ch FTM2 channels (internal) 2-ch 2-ch 2-ch KBI pins GPIO 1.2 MCU block diagram The block diagram below shows the structure of the MCUs. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 25: System Clock Distribution

    1.3 System clock distribution These series contain three on-chip clock sources: • Internal clock source (ICS) module — The main clock source generator providing bus clock and other reference clocks to peripherals MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 26 (DCO) of the ICS when the ICS is configured to run off of the internal or external reference clock. Development tools can select this internal self-clocked source (8 MHz) to speed up BDC communications in systems where the bus clock is slow. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 27 TCLK0 must be limited to 1/4th frequency of the bus clock for synchronization. • TCLK1 — This is an optional external clock source for the FTM1 module. The TCLK1 must be limited to 1/4th frequency of the bus clock for synchronization. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 28 System clock distribution MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 29: Pins And Connections

    PTB3/KBI0P7/TCLK1/ADP7 PTC3 PTC0 PTC2 PTC1 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 2-1. MC9S08PA4 20-pin SOIC package PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA5/IRQ/FTM1CH0/RESET PTA4/ACMPO/BKGD/MS PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3 PTB7/EXTAL PTB0/KBI0P4/RxD0/TCLK0/ADP4 PTB6/XTAL...

  • Page 30: Pin Functions

    0.1 µF ceramic bypass capacitor located as near to the paired V and V power pins as practical to suppress high-frequency noise. V ss 0.1 F Figure 2-4. Power supply bypassing MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 31: Oscillator (Xtal, Extal)

    C1 and C2 (which are usually the same size). As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 32: External Reset Pin (Reset) And Interrupt Pin (Irq)

    IRQ interrupt and is also the input for the BIH and BIL instructions. IRQ is asynchronous external interrupt pins. In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See the following figure for example. PTA5/IRQ/FTM1CH0/RESET 4.7k Figure 2-6. PTA5/IRQ/FTM1CH0/RESET external RC filter MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 33: Background/Mode Select (Bkgd/Ms)

    Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall time on the BKGD pin. PTA5/IRQ/FTM1CH0/RESET Optional Manual Reset BKGD/MS Figure 2-7. Typical debug circuit MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 34: Port A Input/Output (I/O) Pins (Pta5-Pta0)

    When high current function is enabled, PTB4 and PTB5 can drive output current. Each high current drive pin can drive higher sink/source current than the other normal pins, please refer to data sheet for the drive capacity. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 35: Peripheral Pinouts

    — PTB1 KBI0P5 TxD0 — ADP5 — PTB0 KBI0P4 RxD0 TCLK0 ADP4 PTA3 KBI0P3 FTM0CH1 TxD0 ADP3 PTA2 KBI0P2 FTM0CH0 RxD0 ADP2 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 36 Disable all modules that share a pin before enabling another module. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 37: Power Management

    This is the normal operating mode. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE: 0xFFFF after reset. The power supply is fully regulating and all peripherals can be active in run mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 38: Wait Mode

    MCU taking the appropriate interrupt vector. The LPO (≈1 kHz) for the real-time counter clock allows a wakeup from stop3 mode with no external components. When RTC_SC2[RTCPS] is clear, the real-time counter clock function is disabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 39: Lvd Enabled In Stop Mode

    The following table shows the low power mode behaviors. Table 3-1. Low power mode behavior Mode Wait Stop3 Full regulation Full regulation Loose regulation Optional on Optional on Standby Standby FLASH Standby Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 40: Low Voltage Detect (Lvd) System

    LVD is disabled upon entering the stop modes unless the SPMSC1[LVDSE] bit is set or active BDM enabled (BDCSCR[ENBDM]=1). If SPMSC1[LVDSE] and SPMSC1[LVDE] are both set, the current consumption in stop3 with the LVD enabled will be greater. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 41: Power-On Reset (Por) Operation

    (SPMSC1[LVDE] set, SPMSC1[LVWIE] set), SPMSC1[LVWF] will be set and LVW interrupt will occur. There are four user- selectable trip voltages for the LVW upon each LVDV configuration. The trip voltage is selected by SPMSC2[LVWV]. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 42: Bandgap Reference

    LVWIE LVDRE LVDSE LVDE BGBDS BGBE Write LVWACK Reset PMC_SPMSC1 field descriptions Field Description Low-Voltage Warning Flag LVWF The LVWF bit indicates the low-voltage warning status. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 43 Bandgap Buffer Enable BGBE This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. Bandgap buffer disabled. Bandgap buffer enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 44: System Power Management Status And Control 2 Register (Pmc_Spmsc2)

    Middle 1 trip point selected (V LVW2 Middle 2 trip point selected (V LVW3 High trip point selected (V LVW4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 45: Memory Map

    The HCS08 core processor can address 64 KB of memory space. The memory map, shown in the following figure, includes: • User flash memory (flash) • MC9S08PA4: 4,096 bytes; 8 pages of 512 bytes each • Random-access memory (RAM) • MC9S08PA4: 512 bytes •...

  • Page 46: Reset And Interrupt Vector Assignments

    0xFFB4:FFB5 KBI0 Vkbi0 0xFFB6:FFB7 Reserved Reserved 0xFFB8:FFB9 Vrtc 0xFFBA:FFBB Reserved Reserved 0xFFBC:FFBD Reserved Reserved 0xFEBE:FFBF Reserved Reserved 0xFFC0:FFC1 Reserved Reserved 0xFFC2:FFC3 Reserved Reserved 0xFFC4:FFC5 Reserved Reserved Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 47: Register Addresses And Bit Assignments

    4.3 Register addresses and bit assignments The register definitions vary in different memory sizes. The register addresses of unused peripherals are reserved. The following table shows the register availability of the devices. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 48 This leaves room in the direct page for more frequently used registers and variables. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in a direct-page register. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 49 Bit 0 0x002B Reserved — — — — — — — — 0x002C ACMP_CS HYST ACIE ACOPE ACMOD 0x002D ACMP_C0 — — ACPSEL — — ACNSEL Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 50 0x300F SCG_C4 ACMP — — — — KBI0 0x3010 DBG_CAH Bit 15 Bit 8 0x3011 DBG_CAL Bit 7 Bit 0 0x3012 DBG_CBH Bit 15 Bit 8 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 51 Bit 8 0x3033 WDOG_CNTL Bit 7 Bit 0 0x3034 WDOG_TOVALH Bit 15 Bit 8 0x3035 WDOG_TOVALL Bit 7 Bit 0 0x3036 WDOG_WINH Bit 15 Bit 8 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 52 — — — — — — 0x307C KBI0_PE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 KBEDG KBEDG KBEDG KBEDG KBEDG KBEDG KBEDG KBEDG 0x307D KBI0_ES Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 53 — 0x30EC PORT_IOFLT0 — — FLTC FLTB FLTA 0x30ED Reserved — — — — — — — — 0x30EE PORT_IOFLT2 — — — — FLTKBI0 FLTRST Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 54 — — — — 0xFF7B Reserved — — — — — — — — FPOPE 0xFF7C NV_FPROT — FPHDIS — — — DPOPE 0xFF7D NV_EEPROT — Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 55: Random-Access Memory (Ram)

    LDHX #RamLast+1 ;point one past RAM ;SP<-(H:X-1) When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or code executing from non-secure memory. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 56: Flash And Eeprom

    Simultaneous EEPROM memory are implemented with error correction codes (ECC) that can resolve single bit faults and detect double bit faults. The following figure shows the block diagram of the flash and EEPROM module. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 57 • No external high-voltage power supply required for flash memory program and erase operations • Interrupt generation on flash command completion and flash error detection • Security mechanism to prevent unauthorized access to the flash memory MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 58: Function Descriptions

    Not all flash are available to users because some addresses are overlapped with RAM, EEPROM, and registers. MC9S08PA4 contains a piece of 4 KB flash that is fully available for users. This flash block is divided into 8 sectors of 512 bytes.

  • Page 59: Flash And Eeprom Initialization After System Reset

    3. Execute valid flash and EEPROM commands according to MCU functional mode and MCU security state. The figure below shows a general flowchart of the flash or EEPROM command write sequence. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 60 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for CCIF Set? Command Completion Check Figure 4-3. Generic flash and EEPROM command write sequence flowchart MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 61 Setting FCLKDIV[FDIV] too high can destroy the flash and EEPROM memory due to overstress. Setting FCLKDIV[FDIV] too low can result in incomplete programming or erasure of the flash and EEPROM memory cells. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 62 CCOB array contains the command code, followed by the parameters for this specific flash command. For details on the FCCOB settings required by each command, see the flash command descriptions in Flash and EEPROM command summary MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 63 0x06 Program flash 0x07 Program once 0x08 Erase all block 0x09 Erase flash block 0x0A Erase flash sector 0x0B Unsecure NVM 0x0C Verify backdoor access key Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 64: Flash And Eeprom Interrupts

    DFDIF and SFDIF flags in combination with the FERSTAT[DFDIE] and FERSTAT[SFDIE] interrupt enable bits to generate the flash error interrupt request. The logic used for generating the flash module interrupts is shown in the following figure. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 65: Protection

    Default protection settings as well as security information that allows the MCU to restrict access to the flash module are stored in the flash configuration field as described in the table below. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 66 1. For range size, seeTable The flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 67 Table 4-14. Flash protection higher address range FPHS[1:0] Global address range Protected size 0xFC00 – 0xFFFF 1 Kbytes 0xF800 – 0xFFFF 2 Kbytes 0xF400 – 0xFFFF 3 Kbytes 0xF000 – 0xFFFF 4 Kbytes MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 68: Security

    The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys, which are four 16-bit words programmed at addresses 0xFF70–0xFF77. If the KEYEN[1:0] bits are in the enabled MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 69 0xFF70–0xFF77 in the flash configuration field. 4.5.2.7.2 Unsecuring the MCU using BDM A secured MCU can be unsecured by using the following method to erase the flash and EEPROM memory: MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 70: Flash And Eeprom Commands

    Program a dedicated 64 byte field in the nonvolatile information register in flash 0x07 Program once block that is allowed to be programmed only once 0x08 Erase all block Erase all flash and EEPROM blocks Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 71 Verify that a given number of bytes starting at the address provided are erased. Section 0x11 Program EEPROM Program up to four bytes in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 72: Flash And Eeprom Command Summary

    FERSTAT[SFDIF] and FERSTAT[DFDIF] flags will be set. If the FSTAT[ACCERR] or FSTAT[FPVIOL] bits are set, the user must clear these bits before starting any command write sequence. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 73 Table 4-21. Erase verify block command FCCOB requirements CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters 0x02 Global address [23:16] to identify Flash block Global address [15:0] in flash block to be verified MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 74 FSTAT[MGSTAT] bits will be set. Table 4-24. Erase verify flash section command error handling Register Error bit Error condition FSTAT ACCERR Set if CCOBIX[2:0] != 010 at command launch Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 75 Valid phrase index values for the read once command range from 0x0000 to 0x0007. During execution of the read once command, any attempt to read addresses within flash block will return invalid data. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 76 Set if CCOBIX[2:0] ≠ 011 or 101 at command launch NVM_FSTAT ACCERR Set if command not available in current mode (see Table 4-9) Set if an invalid global address [23:0] is supplied (see Table 4-6) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 77 Valid phrase index values for the program once command range from 0x0000 to 0x0007. During execution of the program once command, any attempt to read addresses within flash will return invalid data. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 78 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 1. As found in the memory map for NVM MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 79 Upon clearing FSTAT[CCIF] to launch the erase flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. The FSTAT[CCIF] flag will be set after the erase flash sector operation has completed. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 80 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 1. As found in the memory map for NVM MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 81 Set if an incorrect backdoor key is supplied ACCERR Set if backdoor key access has not been enabled (KEYEN[1:0] ≠ 10 NVM_FSTAT Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 82 Level description (CCOBIX = 010) 0x0000 Return to normal level 0x0001 User margin-1 level 0x0002 User margin-0 level 1. Read margin to the erased state 2. Read margin to the programmed state MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 83 Error bit Error condition Set if CCOBIX[2:0] ≠ 010 at command launch FSTAT ACCERR Set if command is not available in current mode (see Table 4-9) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 84 Table 4-47. Program EEPROM command error handling Register Error Bit Error condition Set if CCOBIX[2:0] < 010 at command launch NVM_FSTAT ACCERR Set if CCOBIX[2:0] >101 at command launch Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 85 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 86: Flash And Eeprom Registers Descriptions

    The FCLKDIV register is used to control timed events in program and erase algorithms. NOTE The FCLKDIV register must not be written while a flash command is executing (NVM_FSTAT[CCIF] = 0) Address: 3020h base + 0h offset = 3020h Read FDIVLD FDIVLCK FDIV Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 87: Flash Security Register (Nvm_Fsec)

    The KEYEN[1:0] bits define the enabling of backdoor key access to the flash module. NOTE: 01 is the preferred KEYEN state to disable backdoor key access. Disabled Disabled Enabled Disabled Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 88: Flash Ccob Index Register (Nvm_Fccobix)

    The FCNFG register enables the flash command complete interrupt and forces ECC faults on flash array read access from the CPU. Address: 3020h base + 4h offset = 3024h Read CCIE IGNSF FDFD FSFD Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 89: Flash Error Configuration Register (Nvm_Fercnfg)

    SFDIE interrupt enable in the FERCNFG register is set. 4.6.5 Flash Error Configuration Register (NVM_FERCNFG) The FERCNFG register enables the flash error interrupts for the FERSTAT flags. Address: 3020h base + 5h offset = 3025h Read DFDIE SFDIE Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 90: Flash Status Register (Nvm_Fstat)

    The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 91: Flash Error Status Register (Nvm_Ferstat)

    The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation returning invalid data was Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 92: Flash Protection Register (Nvm_Fprot)

    FPVIOL bit will be set in the FSTAT register. The block erase of a flash block is not possible if any of the flash sectors contained in the same flash block are protected. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 93: Eeprom Protection Register (Nvm_Eeprot)

    During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the flash configuration field at global address 0xFF7D located in flash memory. To change the EEPROM protection that MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 94: Flash Common Command Object Register:high (Nvm_Fccobhi)

    The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte-wide reads and writes are allowed to the FCCOB register. Address: 3020h base + Ah offset = 302Ah Read CCOB Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 95: Flash Common Command Object Register: Low (Nvm_Fccoblo)

    0xFF7E located in flash memory as indicated by reset condition. Address: 3020h base + Ch offset = 302Ch Read Write Reset * Notes: • x = Undefined at reset. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 96 The NV[7:0] bits are available as nonvolatile bits. During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 97: Interrupt

    While the CPU is responding to the interrupt, the I bit is automatically set to prevent another interrupt from interrupting the ISR itself, which is called nesting of interrupts. Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 98: Interrupt Stack Frame

    CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 99: Interrupt Vectors, Sources, And Local Masks

    (I bit in the CCR) is 0, the CPU finishes the current instruction, stacks the PCL, PCH, X, A, and CCR CPU registers, sets the I bit, and then fetches the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 100 CH1IE FTM0 channel 1 0xFFDE:FFDF Vftm0ch0 FTM0CH0 CH0F CH0IE FTM0 channel 0 0xFFE0:FFE1 Vftm1ovf FTM1 TOIE FTM1 overflow 0xFFE2:FFE3 Vftm1ch1 FTM1CH1 CH1F CH1IE FTM1 channel 1 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 101: Hardware Nested Interrupt

    This device has interrupt priority controller (IPC) module to provide up to four-level nested interrupt capability. IPC includes the following features: • Four-level programmable interrupt priority for each interrupt source. • Support for prioritized preemptive interrupt service routines MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 102 • Interrupt priority mask can be modified during main flow or interrupt service execution. • Previous interrupt mask level is automatically stored when interrupt vector is fetched (four levels of previous values accommodated) MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 103: Interrupt Priority Level Register

    The IPC consists of three major functional blocks: • The interrupt priority level registers • The interrupt priority level comparator set • The interrupt mask register update and restore mechanism MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 104: Interrupt Priority Level Comparator Set

    IPM. If the last position of IPMPS is written, the PSF flag indicates that the IPMPS is full. If all the values in the IPMPS were read, the PSE flag indicates that the IPMPS is empty. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 105: Integration And Application Of The Ipc

    • Before leaving the interrupt service routine, the previous levels must be restored manually by setting PULIPM bit. Watch out for the full (PSF) bit and empty (PSE) bit. 5.2 IRQ The IRQ (external interrupt) module provides a maskable interrupt input. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 106: Features

    When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so that the IRQ, if enabled, can wake the MCU. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 107: Pin Configuration Options

    IRQ pin remains at the asserted level. Interrupt pin request register IRQ memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Interrupt Pin Request Status and Control Register (IRQ_SC) 5.3.1/108 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 108: Interrupt Pin Request Status And Control Register (Irq_Sc)

    Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 109: Interrupt Priority Control Register

    3056 Interrupt Level Setting Registers n (IPC_ILRS6) 5.4.3/111 3057 Interrupt Level Setting Registers n (IPC_ILRS7) 5.4.3/111 3058 Interrupt Level Setting Registers n (IPC_ILRS8) 5.4.3/111 3059 Interrupt Level Setting Registers n (IPC_ILRS9) 5.4.3/111 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 110: Ipc Status And Control Register (Ipc_Sc)

    (ILRxx) value that is greater than or equal to the value of IPM will be presented to the CPU. Writes to this field are allowed, but doing this will not push information to the Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 111: Interrupt Priority Mask Pseudo Stack Register (Ipc_Ipmps)

    (ILRSn is ILRS0 through ILRS9). Address: 3Eh base + 3012h offset + (1d × i), where i=0d to 9d Read ILRn3 ILRn2 ILRn1 ILRn0 Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 112 Interrupt Level Register for Source n*4+1 ILRn1 This field sets the interrupt level for interrupt source n*4+1. ILRn0 Interrupt Level Register for Source n*4+0 This field sets the interrupt level for interrupt source n*4+0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 113: System Control

    (SP) and system control settings. SP is forced to 0x00FF at reset. This device has the following sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Watchdog (WDOG) timer • Illegal opcode detect (ILOP) MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 114: System Options

    PTA5, IRQ, or FTM1CH0. 6.4.3 SCI0 pin reassignment After reset, SCI0 module pinouts of RxD and TxD are mapped on PTB0 and PTB1, respectively. SYS_SOPT1[SCI0PS] bit enables to reassign SCI0 pinouts on PTA2 and PTA3. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 115: Ftm0 Channels Pin Reassignment

    FTMCHS TXDME RXDFE SCI0 RxD0 TxD0 FTM0 FTM0CH1 FTM1CH0 FTM1 FTM1CH1 ACIC RXDCE RTCC ADHWT Figure 6-1. System interconnection diagram MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 116: Acmp Output Selection

    FTM0 channel 1, and the FTM0CH1 pin is released to other shared functions regardless of the configuration of FTM0 pin reassignment. When this bit is clear, the RxD0 pin is connected to SCI0 only. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 117: Sci0 Rxd Filter

    RTC overflow may be captured by FTM1 channel 1 by setting SYS_SOPT2[RTCC] bit. When this bit is set, the RTC overflow is connected to FTM1 channel 1 for capture, the FTM1CH1 pin is released to other shared functions. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 118: Adc Hardware Trigger

    System Options Register 2 (SYS_SOPT2) 6.6.6/124 3006 System Options Register 3 (SYS_SOPT3) 6.6.7/125 304A Illegal Address Register: High (SYS_ILLAH) Undefined 6.6.8/126 304B Illegal Address Register: Low (SYS_ILLAL) Undefined 6.6.9/126 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 119: System Reset Status Register (Sys_Srs)

    (LVR) status bit is also set to indicate that the reset occurred while the internal supply was below the LVR threshold. NOTE: This bit POR to 1, LVR to uncertain value and reset to 0 at any other conditions. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 120 NOTE: This bit reset to 1 on POR and LVR and reset to 0 on other reset. Reset not caused by LVD trip or POR. Reset caused by LVD trip or POR. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 121: System Background Debug Force Reset Register (Sys_Sbdfr)

    HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. Address: 3000h base + 2h offset = 3002h Read Reserved Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 122: System Device Identification Register: Low (Sys_Sdidl)

    Read SCI0PS FTM1PS FTM0PS BKGDPE RSTPE FWAKE STOPE Write Reset SYS_SOPT1 field descriptions Field Description SCI0 Pin Select SCI0PS This write-once bit selects the SCI0 pinouts. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 123 This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset occurs. Stop mode disabled. Stop mode enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 124: System Options Register 2 (Sys_Sopt2)

    This bit allows the Real-time Counter (RTC) overflow to be captured by FTM1 channel 1. RTC overflow is not connected to FTM1 input channel 1. RTC overflow is connected to FTM1 input channel 1. ADHWTS ADC Hardware Trigger Source Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 125: System Options Register 3 (Sys_Sopt3)

    FTM1 channel 0 is selected for the ADC hardware trigger. FTM1 channel 1 is selected for the ADC hardware trigger. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 126: Illegal Address Register: High (Sys_Illah)

    The SYS_ILLAL is a read-only register containing the low 8-bit of the illegal address of ILAD reset. Address: 3000h base + 4Bh offset = 304Bh Read ADDR[7:0] Write Reset * Notes: • x = Undefined at reset. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 127: Universally Unique Identifier Register 1 (Sys_Uuid1)

    The read-only SYS_UUIDx registers contain a series of 63-bit number to identify the unique device in the family. Address: 3000h base + F9h offset = 30F9h Read ID[55:48] Write Reset * Notes: • x = Undefined at reset. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 128: Universally Unique Identifier Register 3 (Sys_Uuid3)

    Address: 3000h base + FBh offset = 30FBh Read ID[39:32] Write Reset * Notes: • x = Undefined at reset. SYS_UUID4 field descriptions Field Description ID[39:32] Universally Unique Identifier MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 129: Universally Unique Identifier Register 5 (Sys_Uuid5)

    Address: 3000h base + FDh offset = 30FDh Read ID[23:16] Write Reset * Notes: • x = Undefined at reset. SYS_UUID6 field descriptions Field Description ID[23:16] Universally Unique Identifier MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 130: Universally Unique Identifier Register 7 (Sys_Uuid7)

    Address: 3000h base + FFh offset = 30FFh Read ID[7:0] Write Reset * Notes: • x = Undefined at reset. SYS_UUID8 field descriptions Field Description ID[7:0] Universally Unique Identifier MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 131: Parallel Input/Output

    • internal pullups disabled (PTxPEn = 0). Additionally, the parallel I/O that support high drive capability are disabled (HDRVE = 0x00) after reset. The following three figures show the structures of each I/O pin. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 132 Introduction PTxPEn PTxOEn PTxDn PTxIEn CPU read PTxDn Figure 7-1. Normal I/O structure PTxPEn PTxOEn PTxDn PTxIEn CPU read PTxDn HDRVE Figure 7-2. High drive I/O structure MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 133: Port Data And Data Direction

    I/O control logic, or by any shared peripheral function, regardless of the state of the corresponding pullup enable register bit. The internal pullup device is also disabled if the pin is controlled by an analog function. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 134: Input Glitch Filter Setting

    Port A Data Register (PORT_PTAD) 7.7.1/135 Port B Data Register (PORT_PTBD) 7.7.2/136 Port C Data Register (PORT_PTCD) 7.7.3/136 30AF Port High Drive Enable Register (PORT_HDRVE) 7.7.4/137 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 135: Port A Data Register (Port_Ptad)

    MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out of the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 136: Port B Data Register (Port_Ptbd)

    MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out of the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 137: Port High Drive Enable Register (Port_Hdrve)

    This read/write bit enables the port A pin as an output. Output Disabled for port A bit 5. Output Enabled for port A bit 5. Output Enable for Port A Bit 4 PTAOE4 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 138: Port B Output Enable Register (Port_Ptboe)

    This read/write bit enables the port B pin as an output. Output Disabled for port B bit 7. Output Enabled for port B bit 7. Output Enable for Port B Bit 6 PTBOE6 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 139: Port C Output Enable Register (Port_Ptcoe)

    Output Disabled for port B bit 0. Output Enabled for port B bit 0. 7.7.7 Port C Output Enable Register (PORT_PTCOE) Address: 0h base + 30B2h offset = 30B2h Read PTCOE3 PTCOE2 PTCOE1 PTCOE0 Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 140: Port A Input Enable Register (Port_Ptaie)

    PTAIE5 This read/write bit enables the port A pin as an input. Input disabled for port A bit 5. Input enabled for port A bit 5. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 141: Port B Input Enable Register (Port_Ptbie)

    Input enabled for port B bit 7. Input Enable for Port B Bit 6 PTBIE6 This read/write bit enables the port B pin as an input. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 142: Port C Input Enable Register (Port_Ptcie)

    Input disabled for port B bit 0. Input enabled for port B bit 0. 7.7.10 Port C Input Enable Register (PORT_PTCIE) Address: 0h base + 30BAh offset = 30BAh Read PTCIE3 PTCIE2 PTCIE1 PTCIE0 Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 143: Port Filter Register 0 (Port_Ioflt0)

    This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–4 Filter selection for input from PTC FLTC BUSCLK FLTDIV1 Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 144: Port Filter Register 2 (Port_Ioflt2)

    FLTRST Filter selection for input from RESET/IRQ No filter. Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically. Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically. FLTDIV3 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 145: Port Clock Division Register (Port_Fclkdiv)

    Filter Division Set 2 FLTDIV2 Port Filter Division Set 2 BUSCLK/32. BUSCLK/64. BUSCLK/128. BUSCLK/256. BUSCLK/512. BUSCLK/1024. BUSCLK/2048. BUSCLK/4096. FLTDIV1 Filter Division Set 1 Port Filter Division Set 1 BUSCLK/2. BUSCLK/4. BUSCLK/8. BUSCLK/16. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 146: Port A Pullup Enable Register (Port_Ptape)

    This control bit determines if the internal pullup device is enabled for the associated PTA pin. For port A pins that are configured as outputs or Hi-Z, these bits have no effect. Pullup disabled for port A bit 0. Pullup enabled for port A bit 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 147: Port B Pullup Enable Register (Port_Ptbpe)

    Hi-Z, these bits have no effect. Pullup disabled for port B bit 2. Pullup enabled for port B bit 2. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 148: Port C Pullup Enable Register (Port_Ptcpe)

    This control bit determines if the internal pullup device is enabled for the associated PTC pin. For port C pins that are configured as outputs or Hi-Z, these bits have no effect. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 149 This control bit determines if the internal pullup device is enabled for the associated PTC pin. For port C pins that are configured as outputs or Hi-Z, these bits have no effect. Pullup disabled for port C bit 0. Pullup enabled for port C bit 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 150 Port data registers MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 151: Clock Management

    The low-power oscillator (LPO) module is an on-chip low-power oscillator providing 1 kHz reference clock to RTC and watchdog (WDOG). The following figures show the block diagram, highlighting the clock modules. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 152: Internal Clock Source (Ics)

    (FLL) as a clock source that is controllable by an internal or external reference clock. The module can provide this FLL clock or the internal reference clock as a source for the MCU system clock, ICSCLK. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 153: Function Description

    • FLL lock detector and external clock monitor • FLL lock detector with interrupt capability • External reference clock monitor with reset capability 8.2.1 Function description The following figure shows the ICS block diagram. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 154: Bus Frequency Divider

    ICSIRCLK, which can be used as an additional clock source. To re-target the ICSIRCLK frequency, write a new value to the ICS_C3[SCTRIM] and ICS_C4[SCFTRIM] bits to trim the period of the internal reference clock: MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 155: Fixed Frequency Clock (Icsffclk)

    • BDIV=000 (divide by 1), RDIV ≥ 010 • BDIV=001 (divide by 2), RDIV ≥ 011 • BDIV=010 (divide by 4), RDIV ≥ 100 • BDIV=011 (divide by 8), RDIV ≥ 101 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 156: Bdc Clock

    There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. The following figure shows the seven states of the ICS as a state diagram. The arrows indicate the allowed movements between the states. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 157: Fll Engaged Internal (Fei)

    FLL engaged internal (FEI) is the default mode of operation and is entered when all of the following conditions occur: • ICS_C1[CLKS] bits are written to 0b • ICS_C1[IREFS] bit is written to 1b MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 158: Fll Engaged External (Fee)

    The FLL clock is controlled by the internal reference clock, and the FLL loop locks the FLL frequency to the 512 times the internal reference frequency. The ICSLCLK will be available for BDC communications, and the internal reference clock is enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 159: Fll Bypassed External (Fbe)

    8.2.2.6 FLL bypassed external low power (FBELP) The FLL bypassed external low power (FBELP) mode is entered when all of the following conditions occur: • ICS_C1[CLKS] bits are written to 10 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 160: Stop (Stop)

    The DCO frequency changes from the pre-stop value to its reset value and the FLL need to re-acquire the lock before the frequency is stable. Timing sensitive operations must wait for the FLL acquisition time, t , before executing. Aquire MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 161: Fll Lock And Clock Monitor

    8.3 Initialization / application information This section provides example code to give some basic direction to a user on how to initialize and configure the ICS module. The example software is implemented in C language. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 162: Initializing Fei Mode

    (ICS_OSCINIT == 0); /* waiting until oscillator is ready */ ICS_C1 = 0x10; /* external clock reference (31.25kHz) to FLL, RDIV = 2, external prescalar = 128 */ ICS_C2 = 0x20; /* BDIV = 1, prescalar = 2 */ MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 163: Initializing Fbe Mode

    The oscillator module provides the reference clock for internal reference clock module (ICS), the real time counter clock module, and other MCU sub-systems. OSCINIT Initialization Oscillator High Gain XTLCLK Oscillator RANGE Low-Powe r OSCOS OSCOUT EXTAL XTAL Figure 8-4. Oscillator module block diagram MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 164: Bypass Mode

    ICS_OSCSC[HGO] = 0, the series resistor R is not used. The feedback resistor R must be carefully selected to get best performance. The figure below shows the typical OSC low-gain mode connection. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 165: High-Gain Configuration

    OSC high-gain mode connection. EXTAL XTAL Figure 8-7. OSC high-gain mode connection 8.3.5.4 Initializing external oscillator for peripherals The following code segment demonstrates initializing external oscillator. Example: 8.3.5.4.1 External oscillator initialization routine MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 166: Khz Low-Power Oscillator (Lpo)

    In stop modes, the bus clock is disabled for all gated peripherals, regardless of the setting in SCG_Cx registers. 8.6 ICS control registers MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 167: Ics Control Register 1 (Ics_C1)

    Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. RDIV ICS_OSCSC[RANGE]= 0 ICS_OSCSC[RANGE]= 1 1024 Reserved Reserved Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 168: Ics Control Register 2 (Ics_C2)

    Encoding 4 - Divides selected clock by 16. Encoding 5 - Divides selected clock by 32. Encoding 6 - Divides selected clock by 64. Encoding 7 - Divides selected clock by 128. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 169: Ics Control Register 3 (Ics_C3)

    Loss of Lock Interrupt LOLIE Determines if an interrupt request is made following a loss of lock indication. The LOLIE bit has an effect only when LOLS is set. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 170: Ics Status Register (Ics_S)

    IREFS, RDIV[2:0], or, if in FEI or FBI modes, TRIM[7:0] will cause the lock status bit to clear and stay cleared until the FLL has reacquired lock. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 171: Osc Status And Control Register (Ics_Oscsc)

    Reset ICS_OSCSC field descriptions Field Description OSC Enable OSCEN The OSCEN bit enables the external clock for use as ICSERCLK. OSC module disabled. OSC module enabled. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 172: System Clock Gating Control Registers

    System Clock Gating Control 1 Register (SCG_C1) 8.7.1/173 300D System Clock Gating Control 2 Register (SCG_C2) 8.7.2/174 300E System Clock Gating Control 3 Register (SCG_C3) 8.7.3/175 300F System Clock Gating Control 4 Register (SCG_C4) 8.7.4/175 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 173: System Clock Gating Control 1 Register (Scg_C1)

    This read-only field is reserved and always has the value 0. RTC Clock Gate Control This bit controls the clock gate to the RTC module. Bus clock to the MTRTCIM1 module is disabled. Bus clock to the RTC module is enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 174: System Clock Gating Control 2 Register (Scg_C2)

    Bus clock to the IPC module is disabled. Bus clock to the IPC module is enabled. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 175: System Clock Gating Control 3 Register (Scg_C3)

    MCU's run and wait currents. NOTE User software should disable the peripheral before disabling the clocks to the peripheral. When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 176 This read-only field is reserved and always has the value 0. KBI0 Clock Gate Control KBI0 This bit controls the clock gate to the KBI0 module. Bus clock to the KBI0 module is disabled. Bus clock to the KBI0 module is enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 177: Chip Configurations

    The trigger can also provide extended breakpoint capacity. The on-chip ICE system is optimized for the HCS08 8-bit architecture and supports 64 KB of memory space. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 178: System Modules

    The low-power oscillator (LPO) module is an on-chip low-power oscillator providing 1 kHz reference clock to RTC and watchdog (WDOG). The following figures show the block diagram, highlighting the clock modules. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 179 1. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true open drain when working as output. 3. PTB4 and PTB5 can provide high sink/source current drive. Figure 9-1. Device block diagram highlighting clock modules and pins MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 180: Memory

    The on-chip bandgap reference (≈1.2V), which is internally connected to ADC channel, provides independent accuracy reference which will not drop over the full operating voltage even when the operating voltage is falling. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 181: Timers

    PTB0/TCLK0 FTM1 channel 0 PTB4/FTM1CH0 PTA5/FTM1CH0 channel 1 PTB5/FTM1CH1 alternate clock PTB3/TCLK1 FTM2 channel 0 — channel 1 — The following figure shows the device block diagram highlighting FTM modules and pins. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 182: Ftm0 Interconnection

    SCI0 TxD signal can be modulated by FTM0 channel 0 PWM output. Please refer to SCI0 TxD modulation. SCI0 RxD signal can be tagged by FTM0 channel 1 input capture function. Please refer SCI0 RxD filter. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 183: Ftm1 Interconnection

    ADC module. Furthermore, when the trigger is enabled, RTC can toggle external pin function if the counter overflows. The following figure shows the device block diagram highlighting RTC module and pin. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 184 1. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true open drain when working as output. 3. PTB4 and PTB5 can provide high sink/source current drive. Figure 9-3. Device block diagram highlighting RTC module and pin MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 185: Communication Interfaces

    Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. The following figure shows the device block diagram highlighting SCI modules and pins. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 186: Sci0 Infrared Functions

    Figure 9-4. Device block diagram highlighting SCI modules and pins 9.8.1.1 SCI0 infrared functions 9.8.1.1.1 SCI0 TxD modulation SCI0 TxD output can be modulated by FTM0 channel 0 PWM output. Please refer to SCI0 TxD modulation. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 187: Analog

    ADC for operation within an integrated microcontroller system-on-chip. The ADC channel assignments, alternate clock function, and hardware trigger function are configured as described following sections. The following figure shows device block diagram highlighting ADC module and pins. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 188: Adc Channel Assignments

    Figure 9-5. Device block diagram highlighting ADC module and pins 9.9.1.1 ADC channel assignments The ADC channel assignments for the device are shown in the following table. Reserved channels convert to an unknown value. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 189 10110 AD22 Temperature sensor 10111 AD23 Bandgap 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Reserved 11011 AD27 Reserved 11100 AD28 Reserved 11101 AD29 REFH 11110 AD30 REFL 11111 Module disabled None MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 190: Alternate Clock

    V • Convert the temperature sensor channel (AD22) • By using the calculated value of V , convert the digital value of AD22 into a voltage, V TEMP MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 191: Analog Comparator (Acmp)

    When using the bandgap reference voltage as the reference voltage to the built-in DAC, the user must enable the bandgap buffer by setting BGBE =1 in SPMSC1. For value of bandgap voltage reference see Bandgap reference. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 192 1. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true open drain when working as output. 3. PTB4 and PTB5 can provide high sink/source current drive. Figure 9-6. Device block diagram highlighting ACMP modules and pins MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 193: Acmp Configuration Information

    ACMP module output can be directly ejected to SCI0 RxD. In this mode, SCI0 external RxD pinout does not work. Any external signal tagged to ACMP inputs can be regarded as input pins. Please refer SCI0 RxD filter. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 194: Human-Machine Interfaces Hmi

    This device has one KBI modules with up to 8 keyboard interrupt inputs grouped in a KBI modules available depending on packages. The following figure shows the device block diagram with the KBI modules and pins highlighted. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 195 1. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true open drain when working as output. 3. PTB4 and PTB5 can provide high sink/source current drive. Figure 9-7. Block diagram highlighting KBI modules and pins MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 196 Human-machine interfaces HMI MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 197: Central Processor Unit

    • Relative — 8-bit signed offset to branch destination • Immediate — Operand in next object code byte(s) • Direct — Operand in memory at 0x0000–0x00FF • Extended — Operand anywhere in 64-Kbyte address space MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 198: Programmer's Model And Cpu Registers

    The A accumulator is a general-purpose 8-bit register. One input operand from the arithmetic logic unit (ALU) is connected to the accumulator, and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 199: Index Register (H:x)

    The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 family and is seldom used in new HCS08 V6 programs because it affects only the low-order half of the stack pointer. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 200: Program Counter (Pc)

    TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set. 0 Interrupts enabled Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 201: Addressing Modes

    Effective address computations do not require extra execution cycles. The HCS08 V6 CPU uses the 16 addressing modes described in the following sections. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 202: Inherent Addressing Mode (Inh)

    LDA $55 means to load the value from address $0055 into the accumulator. Without the # symbol, the instruction is erroneously interpreted as a direct addressing instruction. Example: #$55 CPHX #$FFFF LDHX #$67 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 203: Direct Addressing Mode (Dir)

    In extended addressing, the full 16-bit address of the memory location to be operated on is provided in the instruction. Extended addressing can access any location in the 64 KB memory map. Example: MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 204: Indexed Addressing Mode

    The table can begin anywhere and can extend as far as the address map allows. The k value would typically be in H:X, and the address of the beginning of the table would be MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 205: Indexed, 8-Bit Offset With Post Increment (Ix1+)

    The sum is the effective address of the operand. If interrupts are disabled, this addressing mode allows the stack pointer to be used as a second "index" register. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 206: Sp-Relative, 16-Bit Offset (Sp2)

    This addressing mode is used to move an 8-bit constant to any location in the direct page memory. The source data is the byte immediately following the opcode, and the destination is addressed by the second byte following the opcode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 207: Indexed To Direct, Post Increment

    CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 208: Wait Mode

    MCU operation during software development. Active background mode is entered in any of the following ways: • When the BKGD/MS pin is low at the time the MCU exits reset. • When a BACKGROUND command is received through the BKGD pin. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 209: Security Mode

    Core. The core receives an external input signal that, when asserted, informs to the core that the MCU is in secure mode. While in secure mode, the core controls the following set of conditions: MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 210 Table 10-2. Security conditions for read access Inputs conditions Read control Ram, flash or Security Program or Current CPU instruction Current access Read access EEPROM enabled vector read from secure memory is via BDC allowed access MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 211: Hcs08 V6 Opcodes

    (SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 212: Instruction Set Summary

    – ↕ ↕ ↕ ↕ ↕ ADC oprx16,SP – 9ED9 ee ff ↕ ↕ ↕ ↕ ↕ ADC oprx8,SP – 9EE9 ↕ ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 213 BCC rel Branch if Carry Bit Branch if (C) = 0 – – – – – – Clear – – – – – – DIR (b0) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 214 ↕ BIT ,X − − − ↕ ↕ BIT oprx16,SP − − − 9ED5 ee ff ↕ ↕ BIT oprx8,SP − − − 9EE5 ↕ ↕ Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 215 ↕ – – – – – – DIR (b0) – – – – – – DIR (b1) – – – – – – DIR (b2) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 216 Memory Updated But Operands Not Changed) CMP ,X – – ↕ ↕ ↕ ↕ CMP oprx16,SP – – 9ED1 ee ff ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 217 ↕ ↕ A ← (A) – 0x01 DECA − − − ↕ ↕ ↕ X ← (X) – 0x01 DECX − − − ↕ ↕ ↕ Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 218 LDA #opr8i − − − ↕ ↕ LDA opr8a LDA opr16a hh ll LDA oprx16,X ee ff A ← (M) Load Accumulator LDA oprx8,X from Memory Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 219 − − 9E64 ↕ ↕ ↕ − − − DIR/DIR ↕ ↕ opr8a,opr8a ← (M) MOV opr8a,X+ Move − − − DIR/IX+ ↕ ↕ destination source Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 220 − − − − − − Low) from Stack Pull (X) ROL opr8a − − ↕ ↕ ↕ ↕ ROLA − − ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 221 ↕ ↕ ↕ C ← 1 Set Carry Bit − − − − − I ← 1 Set Interrupt Mask Bit − − − − − Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 222 PC ← (PC) + 0x0001 Push (PCL) SP ← (SP) – 0x0001 Push (PCH) SP ← (SP) – 0x0001, Push (X) SP ← (SP) – 0x0001 Push (A) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 223 SP ← (H:X) – 0x0001 Transfer Index − − − − − − Register to SP I bit ← 0, Halt CPU WAIT Enable Interrupts Wait − − − − − for Interrupt MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 224 Instruction Set Summary MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 225: Keyboard Interrupts (Kbi)

    • both rising-edge and high-level sensitivity • One software-enabled keyboard interrupt • Exit from low-power modes 11.1.2 Modes of Operation This section defines the KBI operation in: • Wait mode • Stop mode • Background debug mode MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 226: Kbi In Stop Modes

    The block diagram for the keyboard interrupt module is shown below.. BUSCLK KBACK V DD RESET KBIxP0 KBIPE0 SYNCHRONIZER KBEDG0 STOP BYPASS KEYBOARD STOP INTERRUPT FF KBIx INTERRUPT REQUEST KBIxPn KBMOD KBIPEn KBIE KBEDGn Figure 11-1. KBI block diagram MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 227: External Signals Description

    Section/ address Register name Access Reset value (in bits) page (hex) KBI Status and Control Register (KBI0_SC) 11.4.1/228 307C KBIx Pin Enable Register (KBI0_PE) 11.4.2/228 307D KBIx Edge Select Register (KBI0_ES) 11.4.3/229 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 228: Kbi Status And Control Register (Kbix_Sc)

    Keyboard detects edges only. Keyboard detects both edges and levels. 11.4.2 KBIx Pin Enable Register (KBIx_PE) KBIx_PE contains the pin enable control bits. Address: 3Ch base + 3040h offset = 307Ch Read KBIPE Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 229: Kbix Edge Select Register (Kbix_Es)

    KBIx_SC[KBMOD] bit. Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBIx_ES[KBEDGn] bits. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 230: Edge-Only Sensitivity

    If an internal pullup resistor is enabled for an enabled KBI pin, the associated I/O port pull select register (see I/O Port chapter) can be used to select an internal pullup resistor. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 231: Kbi Initialization

    3. Before using internal pullup resistors, configure the associated bits in PORT_PTxPE. 4. Enable the KBI pins by setting the appropriate KBIx_PE[KBIPEn] bits. 5. Write to KBIx_SC[KBACK] to clear any false interrupts. 6. Set KBIx_SC[KBIE] to enable interrupts. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 232 Functional Description MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 233: Flextimer Module (Ftm)

    12.1.2 Features The FTM features include: • Selectable FTM source clock: • Source clock can be the system clock, the fixed frequency clock, or an external clock MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 234: Modes Of Operation

    MCU from wait mode, the power can then be saved by disabling FTM functions before entering wait mode. 12.1.4 Block diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 235: Signal Description

    Input capture interrupt input CH7F mode logic Output modes C7VH:L channel 7 logic output Figure 12-1. FTM block diagram 12.2 Signal description The following table shows the user-accessible signals for the FTM. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 236: Extclk - Ftm External Clock

    This section provides a detailed description of all FTM registers. 12.3.1 Module memory map This section presents a high-level summary of the FTM registers and how they are mapped. 12.3.2 Register descriptions This section consists of register descriptions in address order. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 237 12.3.8/241 30C6 Channel Value High (FTM2_C0VH) 12.3.9/243 30C7 Channel Value Low (FTM2_C0VL) 12.3.10/244 30C8 Channel Status and Control (FTM2_C1SC) 12.3.8/241 30C9 Channel Value High (FTM2_C1VH) 12.3.9/243 30CA Channel Value Low (FTM2_C1VL) 12.3.10/244 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 238: Status And Control (Ftmx_Sc)

    Selects one of 8 division factors for the clock source selected by CLKS. The new prescaler factor affects the clock source on the next system clock cycle after the new value is updated into the register bits. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 239: Counter High (Ftmx_Cnth)

    BDM became active, it reads the appropriate value from the other half of the 16-bit value after returning to normal execution. Address: Base address + 1h offset Read COUNT_H Write Reset FTMx_CNTH field descriptions Field Description COUNT_H Counter value high byte MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 240: Counter Low (Ftmx_Cntl)

    It is recommended to initialize the FTM counter, by writing to CNTH or CNTL, before writing to the FTM modulo register to avoid confusion about when the first counter overflow will occur. Address: Base address + 3h offset Read MOD_H Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 241: Modulo Low (Ftmx_Modl)

    Toggle Output on match Clear Output on match Set Output on match Edge-aligned PWM High-true pulses (clear Output on match) Low-true pulses (set Output on match) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 242 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 243: Channel Value High (Ftmx_Cnvh)

    BDM was not active. Address: Base address + 6h offset + (3d × i), where i=0d to 1d Read VAL_H Write Reset FTMx_CnVH field descriptions Field Description VAL_H Channel Value High Byte MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 244: Channel Value Low (Ftmx_Cnvl)

    12.4 Functional Description The following sections describe the FTM features. The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 245: Clock Source

    Therefore, to meet the Nyquist criteria and account for jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 246: Prescaler

    The FTM period when using up counting is (MODH:L + 0x0001) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MODH:L to 0x0000. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 247: Up-Down Counting

    The FTM period when using up-down counting is 2 × (MODH:L) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MODH:L to (MODH:L – 1). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 248: Free Running Counter

    12.4.4 Input capture mode The input capture mode is selected when (CPWMS = 0), (MSnB:MSnA = 0:0), and (ELSnB:ELSnA ≠ 0:0). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 249: Output Compare Mode

    CHnF bit is set on the third rising edge of the system clock after a valid edge occurs on the channel input. 12.4.5 Output compare mode The output compare mode is selected when (CPWMS = 0) and (MSnB:MSnA = 0:1). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 250 CNTH:L channel (n) output previous value previous value CHnF bit TOF bit Figure 12-10. Example of the output compare mode when the match sets the channel output MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 251: Edge-Aligned Pwm (Epwm) Mode

    0x0000 is loaded into the FTM counter. Additionally, it is forced low at the channel (n) match, when the FTM counter = CnVH:L. See the following figure. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 252: Center-Aligned Pwm (Cpwm) Mode

    0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MODH:L and then counts down until it reaches the value of 0x0000. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 253 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnVH:L) when counting down, and it is forced high at the channel (n) match when counting up; see the following figure. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 254: Update Of The Registers With Write Buffers

    FTM counter changes from 0xFFFF to 0x0000. • If the selected mode is CPWM mode, then MODH:L registers are updated after both bytes have been written and the FTM counter changes from MODH:L to (MODH:L – 0x0001). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 255: Cnvh:l Registers

    • The FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] = 0b00) • The timer overflow interrupt is zero (Timer overflow interrupt) • The channels interrupts are zero (Channel (n) interrupt) MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 256 (n) output is toggled when there is a match. In the output compare mode, the channel output is not updated to its initial value when there is a write to CNTH or CNTL registers (item 3). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 257: Ftm Interrupts

    The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 12.6.2 Channel (n) interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 258 FTM Interrupts MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 259: Real-Time Counter (Rtc)

    • Software selectable clock sources for input to prescaler with programmable 16 bit prescaler • XOSC 32.768KHz nominal. • LPO (~1 kHz) • Bus clock 13.2.1 Modes of operation This section defines the RTC operation in Stop, Wait, and Background Debug modes. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 260: Wait Mode

    RTCPS Write 1 to RTIF Figure 13-1. Real-time counter (RTC) block diagram 13.3 Register definition The RTC includes a status and control register, a 16-bit counter register, and a 16-bit modulo register. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 261: Rtc Status And Control Register 1 (Rtc_Sc1)

    This read-only field is reserved and always has the value 0. This field is reserved. Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 262: Rtc Status And Control Register 2 (Rtc_Sc2)

    If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048. If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100. If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 263: Rtc Modulo Register: High (Rtc_Modh)

    RTIF bit on each rising edge of the prescaler output. Reset sets the modulo to 0x00. 13.3.5 RTC Counter Register: High (RTC_CNTH) RTC_CNTH, together with RTC_CNTL, indicates the read-only value of the current RTC count of the 16-bit counter. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 264: Rtc Counter Register: Low (Rtc_Cntl)

    The RTC is composed of a main 16-bit up-counter with a 16-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. The module also contains software selectable interrupt logic . MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 265 The RTC allows for an interrupt to be generated whenever RTC_SC1[RTIF] is set. To enable the real-time interrupt, set the Real-Time Interrupt Enable field (RTC_SC1[RTIE]). RTC_SC1[RTIF] is cleared by writing a 1 to RTC_SC1[RTIF]. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 266: Rtc Operation Example

    The example below shows how to implement time of day with the RTC using the XOSC clock source to achieve the lowest possible power consumption. Example: 13.5.1 Software calendar implementation in RTC ISR MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 267 Seconds = 0; /* 60 minutes in an hour */ if (Minutes > 59) Hours++; Minutes = 0; /* 24 hours in a day */ if (Hours > 23) Days ++; Hours = 0; MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 268 Initialization/application information MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 269: Serial Communications Interface (Sci)

    • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 14.1.2 Modes of operation See Section Functional description for details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 270: Block Diagram

    SCI Controls TxD TO TxD Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 14-1. SCI transmitter block diagram The following figure shows the receiver portion of the SCI. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 271 Logic RDRF IDLE ILIE Rx Interrupt Request LBKDIF LBKDIE From RxD Pin Active Edge RXEDGIF Detect RXEDGIE ORIE FEIE Error Interrupt Request NEIE Parity Checking PEIE Figure 14-2. SCI receiver block diagram MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 272: Sci Signal Descriptions

    SCI registers. This section refers to registers and control bits only by their names. An NXP-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 273: Sci Baud Rate Register: High (Scix_Bdh)

    Stop Bit Number Select SBNS SBNS determines whether data characters are one or two stop bits. One stop bit. Two stop bit. Baud Rate Modulo Divisor. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 274: Sci Baud Rate Register: Low (Scix_Bdl)

    14.3.3 SCI Control Register 1 (SCIx_C1) This read/write register controls various optional features of the SCI system. Address: 3080h base + 2h offset = 3082h Read LOOPS SCISWAI RSRC WAKE Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 275 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. Even parity. Odd parity. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 276: Sci Control Register 2 (Scix_C2)

    When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS is set the RxD pin reverts to being a general-purpose I/O pin even if RE is set. Receiver off. Receiver on. Receiver Wakeup Control Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 277: Sci Status Register 1 (Scix_S1)

    • Write to the SCI data register (SCI_D) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SCI_C2[SBK] Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 278 FE set and then read the SCI data register (SCI_D). No framing error detected. This does not guarantee the framing is correct. Framing error. Parity Error Flag Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 279: Sci Status Register 2 (Scix_S2)

    No active edge on the receive pin has occurred. An active edge on the receive pin has occurred. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 280: Sci Control Register 3 (Scix_C3)

    SCI receiver idle waiting for a start bit. SCI receiver active (RxD input not idle). 14.3.7 SCI Control Register 3 (SCIx_C3) Address: 3080h base + 6h offset = 3086h Read TXDIR TXINV ORIE NEIE FEIE PEIE Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 281 Hardware interrupt requested when FE is set. Parity Error Interrupt Enable PEIE This bit enables the parity error flag (PF) to generate hardware interrupt requests. PF interrupts disabled; use polling). Hardware interrupt requested when PF is set. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 282: Sci Data Register (Scix_D)

    Read receive data buffer 0 or write transmit data buffer 0. R0T0 14.4 Functional description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 283: Baud Rate Generation

    14.4.2 Transmitter functional description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 284: Send Break And Queued Idle

    If the receiving device is another NXP SCI, the break characters are received as 0s in all eight data bits and a framing error (SCI_S1[FE] = 1) occurs. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 285: Receiver Functional Description

    (lsb first), and one (or two) stop bits of logic 1. For information about 9-bit data mode, refer to 8- and 9-bit data modes. For the remainder of this discussion, assume the SCI is configured for normal 8-bit data mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 286: Data Sampling Technique

    It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 287: Receiver Wake-Up Operation

    When SCI_C1[ILT] is set, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 288: Interrupts And Status Flags

    When a program detects that the receive data register is full (SCI_S1[RDRF] = 1), it gets the data from the receive data register by reading SCI_D. The SCI_S1[RDRF] flag is cleared by reading SCI_S1 while SCI_S1[RDRF] is set and then reading SCI_D. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 289: Baud Rate Tolerance

    As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 290 The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit and 2 stop bits character with no errors is: ((186 - 179) / 186) X 100 = 3.76% MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 291: Fast Data Tolerance

    The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit and 2 stop bits character with no errors is: ((186 - 192) / 186) x 100 = 3.23% MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 292: Additional Sci Functions

    (including preamble, break and normal data) being transmitted out of or received into the SCI module, that means SCI_S1[TC] =1, SCI_S1[TDRE] = 1, and SCI_S2[RAF] = 0 must all meet before entering stop mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 293: Loop Mode

    In single-wire mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 294 Functional description MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 295: Analog-To-Digital Converter (Adc)

    • Operation in Wait or Stop3 modes for lower noise operation • Asynchronous clock source for lower noise operation • Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 296: Block Diagram

    ADACK ASYNC CLOCK GENERATOR ADICLK ADIV Figure 15-1. ADC Block Diagram 15.2 External Signal Description The ADC module supports up to 24 separate analog inputs. It also requires four supply/ reference/ground connections. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 297: Analog Power (Vdda)

    In some packages, V REFL REFL connected internally to V . If externally available, connect the V pin to the same REFL voltage potential as V MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 298: Adc Control Registers

    ADC_SC4[AFDEP]. Any write 0x1F to these bits will reset the FIFO and stop the conversion if it is active. Address: 10h base + 0h offset = 10h Read COCO AIEN ADCO ADCH Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 299 The ADCH bits form a 5-bit field that selects one of the input channels. 00000-00111 AD0-AD7 01000-10011 10100-10101 Reserved 10110 Temperature Sensor 10111 Bandgap 11000-11100 Reserved 11101 REFH 11110 REFL 11111 Module disabled NOTE: Reset FIFO in FIFO mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 300: Status And Control Register 2 (Adc_Sc2)

    Indicates that ADC result FIFO have at least one valid new data. Indicates that ADC result FIFO have no valid new data. Result FIFO full FFULL Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 301: Status And Control Register 3 (Adc_Sc3)

    Short sample time. Long sample time. 3–2 Conversion Mode Selection MODE MODE bits are used to select between 12-, 10-, or 8-bit operation. 8-bit conversion (N=8) Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 302: Status And Control Register 4 (Adc_Sc4)

    OR all of compare trigger. AND all of compare trigger. 4–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 303: Conversion Result High Register (Adc_Rh)

    AFDEP. The AD result FIFO can be read via ADC_RH:ADC_RL continuously by the order set in analog input channel ADCH. If the MODE bits are changed, any data in ADC_RH becomes invalid. Address: 10h base + 4h offset = 14h Read Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 304: Conversion Result Low Register (Adc_Rl)

    AFDEP. The AD result FIFO can be read via ADC_RH:ADC_RL continuously by the order set in analog input channel FIFO. Address: 10h base + 5h offset = 15h Read Write Reset ADC_RL field descriptions Field Description Conversion Result[7:0] MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 305: Compare Value High Register (Adc_Cvh)

    8 bits of the result following a conversion in 12-bit mode. Address: 10h base + 7h offset = 17h Read Write Reset ADC_CVL field descriptions Field Description Conversion Result[7:0] MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 306: Pin Control 1 Register (Adc_Apctl1)

    AD3 pin I/O control disabled. ADC Pin Control 2 ADPC2 ADPC2 controls the pin associated with channel AD2. AD2 pin I/O control enabled. AD2 pin I/O control disabled. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 307: Functional Description

    The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ADC_SC2[ACFE] bit and operates with any of the conversion modes and configurations. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 308: Clock Select And Divide Control

    • The output buffer is forced to its high impedance state. • The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer disabled. • The pullup is disabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 309: Hardware Trigger

    In software triggered operation, continuous conversions begin after ADC_SC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 310: Completing Conversions

    This indicates a mode of operation change has occurred and the current and rest of conversions (when ADC_SC4[AFDEP] are not all 0s) are therefore invalid. • The MCU is reset. • The MCU enters Stop mode with ADACK not enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 311: Power Control

    Single or first continuous 10-bit or 12-bit 0x, 10 43 ADCK cycles + 5 bus clock cycles Single or first continuous 8-bit 5 µs + 20 ADCK + 5 bus clock cycles Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 312: Automatic Compare Function

    (ADC_CVH and ADC_CVL). When comparing to an upper limit (ADC_SC2[ACFGT] = 1), if the result is greater-than or equal-to the compare value, ADC_SC1[COCO] is set. When comparing to a lower limit (ADC_SC2[ACFGT] = 0), if MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 313: Fifo Operation

    ADC_SC1[ADCH] will re-fill channel FIFO to initial new conversion. It will abort current conversion and any other conversions that did not start. Write to the ADC_SC1 after all the conversions are completed or ADC is in idle state. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 314 FIFO. When all conversions set in the analog input channel FIFO completes, the ADC_SC1[COCO] bit is set and an interrupt request will be submitted to CPU if the ADC_SC1[AIEN] bit is set. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 315 In continuous conversion in which the ADC_SC1[ADCO] bit is set, the ADC starts next conversion immediately when all conversions are completed. ADC module will fetch the analog input channel from the beginning of analog input channel FIFO. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 316 Start FIFOed Conversion when hardware trigger occurs Hardware Triggered Continuous Conversion (Only need one hardware trigger) COCO = 1 The n AD result store Conversions Completed Figure 15-3. ADC FIFO conversion sequence MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 317: Mcu Wait Mode Operation

    If a conversion is in progress when the MCU enters Stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in Stop3 mode by means of the hardware trigger or if continuous conversions are enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 318: Initialization Information

    ADCK. This register is also used for selecting sample time and low-power configuration. 2. Update status and control register 2 (ADC_SC2) to select the hardware or software conversion trigger and compare function options, if enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 319: Pseudo-Code Example

    4. Update status and control register 1 (ADC_SC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 320: Pseudo-Code Example

    = ADC_R; // read conversion result of channel 3 buffer[1] = ADC_R; // read conversion result of channel 5 buffer[2] = ADC_R; // read conversion result of channel 7 buffer[3] = ADC_R; MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 321: Application Information

    If separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the V pin. This should be the only ground connection between these supplies if possible. The V pin makes a good single point ground location. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 322: Analog Input Pins

    REFH REFL is equal to or exceeds V , the converter circuit converts the signal to 0xFFF (full scale REFH 12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 323: Sources Of Error

    System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 324 Four samples are required to eliminate the effect of a 1LSB, one-time error. • Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 325: Code Width And Quantization Error

    0x3FE code width and its ideal (1 lsb) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 326: Code Jitter, Non-Monotonicity, And Missing Codes

    Missing codes are those values that are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 327: Analog Comparator (Acmp)

    • Selectable interrupt on rising edge, falling edge, or both rising or falling edges of comparator output • Selectable inversion on comparator output • Up to four selectable comparator inputs • Operational in Stop3 mode MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 328: Modes Of Operation

    16.1.2.3 Operation in Debug mode When the MCU is in Debug mode, the ACMP continues operating normally. 16.1.3 Block diagram The block diagram of the ACMP module is shown in the following figure. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 329: External Signal Description

    Access Reset value (in bits) page (hex) ACMP Control and Status Register (ACMP_CS) 16.3.1/330 ACMP Control Register 0 (ACMP_C0) 16.3.2/331 ACMP Control Register 1 (ACMP_C1) 16.3.3/331 ACMP Control Register 2 (ACMP_C2) 16.3.4/332 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 330: Acmp Control And Status Register (Acmp_Cs)

    ACMP output can be placed onto external pin. ACMOD ACMP MOD Determines the sensitivity modes of the interrupt trigger. ACMP interrupt on output falling edge. ACMP interrupt on output rising edge. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 331: Acmp Control Register 0 (Acmp_C0)

    ACMP Negative Input Select External reference 0 External reference 1 Reserved DAC output 16.3.3 ACMP Control Register 1 (ACMP_C1) Address: 2Ch base + 2h offset = 2Eh Read DACEN DACREF DACVAL Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 332: Acmp Control Register 2 (Acmp_C2)

    The DAC includes a 64-level DAC (digital to analog converter) and relevant control logic. DAC can select one of two reference inputs, V or on-chip bandgap, as the DAC input V by setting ACMP_C1[DACREF]. After the DAC is enabled, it converts the data MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 333: Setup And Operation Of Acmp

    The two parts of ACMP (DAC and CMP) can be set up and operated independently. But if the DAC works as an input of the CMP, the DAC must be configured before the ACMP is enabled. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 334: Resets

    When in stop3 mode, a valid edge on ACMP output generates an asynchronous interrupt that can wake the MCU from stop3. The interrupt can be cleared by writing a 0 to the ACMP_CS[ACF] bit. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 335: Watchdog (Wdog)

    • Robust write sequence for counter refresh • Refresh sequence of writing 0xA602 and then 0xB480 within 16 bus clocks • Window mode option for the refresh mechanism • Programmable 16-bit window value MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 336: Block Diagram

    Logic Clock Delay Window Compare Logic Protect IRQ Interrupt 0xC520 128 Bus Cycle Control Status 16-bit Window Register Disable Protect Bit Write Control 0xD928 UPDATE PRES WIN Figure 17-1. WDOG block diagram MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 337: Memory Map And Register Definition

    (timeout or illegal write to the watchdog), prior to forcing a reset. After the interrupt vector fetch, the reset occurs after a delay of 128 bus clocks. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 338 Watchdog enabled in chip wait mode. Stop Enable STOP This write-once bit enables the watchdog to operate when the chip is in stop mode. Watchdog disabled in chip stop mode. Watchdog enabled in chip stop mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 339: Watchdog Control And Status Register 2 (Wdog_Cs2)

    This write-once field indicates the clock source that feeds the watchdog counter. See the Clock source section. Bus clock. 1 kHz internal low-power oscillator (LPOCLK). 32 kHz internal oscillator (ICSIRCLK). External clock source. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 340: Watchdog Counter Register: High (Wdog_Cnth)

    CNTHIGH High byte of the Watchdog Counter 17.2.4 Watchdog Counter Register: Low (WDOG_CNTL) See the description of the WDOG_CNTH register. Address: 3030h base + 3h offset = 3033h Read CNTLOW Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 341: Watchdog Timeout Value Register: High (Wdog_Tovalh)

    17.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL) See the description of the WDOG_TOVALH register. NOTE All the bits reset to 0 in read. Address: 3030h base + 5h offset = 3035h Read TOVALLOW Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 342: Watchdog Window Register: High (Wdog_Winh)

    17.2.8 Watchdog Window Register: Low (WDOG_WINL) See the description of the WDOG_WINH register. Address: 3030h base + 7h offset = 3037h Read WINLOW Write Reset WDOG_WINL field descriptions Field Description WINLOW Low byte of Watchdog Window MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 343: Functional Description

    In addition, if window mode is used, software must not start the refresh sequence until after the time value set in the WDOG_WINH and WDOG_WINL registers. See the following figure. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 344: Window Mode

    The refresh write sequence is a write of 0xA602 followed by a write of 0xB480 to the WDOG_CNTH and WDOG_CNTL registers. The write of the 0xB480 must occur within 16 bus clocks after the write of 0xA602; otherwise, the watchdog resets the MCU. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 345: Example Code: Refreshing The Watchdog

    Otherwise, the WDOG uses the reset values by default. If window mode is not used (CS2[WIN] is 0), writing to WDOG_WINH:L is not required to make the new configuration take effect. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 346: Reconfiguring The Watchdog

    WDOG_CNT = 0xD928; // write the 2nd unlock word WDOG_TOVAL = 1000; // setting timeout value WDOG_CS2 = WDOG_CS2_CLK_MASK; // setting 1-kHz clock source WDOG_CS1 = WDOG_CS1_EN_MASK; // enable counter running EnableInterrupts; // enable global interrupt MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 347: Clock Source

    2.5 periods of the previous clock source and 2.5 periods of the new clock source after the configuration time period (128 bus clocks) ends. This delay ensures a smooth transition before restarting the counter with the new configuration. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 348: Using Interrupts To Delay Resets

    • For Stop3 mode, set CS1[STOP]. NOTE The watchdog can not generate interrupt in Stop3 mode even if CS1[STOP] is set and will not wake the MCU from Stop3 mode. It can generate reset during Stop3 mode. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 349: Fast Testing Of The Watchdog

    4. The watchdog counter times out and forces a reset. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 350: Entering User Mode

    As an ongoing test when using the default 1-kHz clock source, software can periodically read the WDOG_CNTH and WDOG_CNTL registers to ensure the counter is being incremented. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 351: Development Support

    • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 352: Background Debug Controller (Bdc)

    • Non-intrusive commands can be executed at any time even while the user's program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 353: Bkgd Pin Description

    If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 354: Communication Details

    Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 355 1 0 C Y C L E S H O S T S A M P L E S B K G D P IN Figure 18-3. BDC target-to-host serial bit timing (logic 1) MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 356: Bdc Commands

    The following table shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in the following table to describe the coding structure of the BDC commands. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 357 TRACE1 Active BDM 10/d Trace 1 user instruction at the address in the PC, then return to active background mode Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 358 • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 359: Bdc Hardware Breakpoint

    Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 360: Comparators A And B

    • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 361: Change-Of-Flow Information

    DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 362: Tag Vs. Force Breakpoints And Triggers

    There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 363: Trigger Modes

    A Then B ̶ Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 364: Hardware Breakpoints

    CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 365: Memory Map And Register Description

    The reset values shown in the register figure are those in the normal reset conditions. If the MCU is reset in BDM, ENBDM, BDMACT, CLKSW will be reset to 1 and others all be to 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 366 BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 367: Bdc Breakpoint Match Register: High (Bdc_Bkpth)

    Breakpoints are normally set while the target MCU is in active background mode before running the user application program. Address: 0h base + 1h offset = 1h Read A[15:8] Write Reset BDC_BKPTH field descriptions Field Description A[15:8] High 8-bit of hardware breakpoint address. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 368: Bdc Breakpoint Register: Low (Bdc_Bkptl)

    BDC_SBDFR field descriptions Field Description 7–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Background Debug Force Reset BDFR Table continues on the next page... MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 369 A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 370 Memory map and register description MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 371: Debug Module (Dbg)

    • Event only B, store data • A then event only B, store data • Inside range, A ≤ address ≤ B • Outside range, address < A or address > B MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 372: Modes Of Operation

    MCU is secure. The DBG module comparators are disabled when executing a Background Debug Mode (BDM) command. 19.1.3 Block diagram The following figure shows the structure of the DBG module. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 373: Signal Description

    Figure 19-1. DBG block diagram 19.2 Signal description The DBG module contains no external signals. 19.3 Memory map and registers This section provides a detailed description of all DBG registers accessible to the end user. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 374: Debug Comparator A High Register (Dbg_Cah)

    Field Description CA[15:8] Comparator A High Compare Bits The Comparator A High compare bits control whether Comparator A will compare the address bus bits [15:8] to a logic 1 or logic 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 375: Debug Comparator A Low Register (Dbg_Cal)

    The Comparator A Low compare bits control whether Comparator A will compare the address bus bits [7:0] to a logic 1 or logic 0. Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 376: Debug Comparator B High Register (Dbg_Cbh)

    DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 3010h base + 3h offset = 3013h Read CB[7:0] Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 377: Debug Comparator C High Register (Dbg_Cch)

    The Comparator C High compare bits control whether Comparator C will compare the address bus bits [15:8] to a logic 1 or logic 0. Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 378: Debug Comparator C Low Register (Dbg_Ccl)

    DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 3010h base + 6h offset = 3016h Read F[15:8] Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 379: Debug Fifo Low Register (Dbg_Fl)

    DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX and DBGFH so it is not necessary to read them before reading DBGFL. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 380: Debug Comparator A Extension Register (Dbg_Cax)

    The RWA bit controls whether read or write is used in compare for Comparator A. The RWA bit is not used if RWAEN = 0. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 381: Debug Comparator B Extension Register (Dbg_Cbx)

    RWBEN = 0.In full modes, RWAEN and RWA are used to control comparison of R/W and RWB is ignored. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 382: Debug Comparator C Extension Register (Dbg_Ccx)

    The RWC bit controls whether read or write is used in compare for Comparator C. The RWC bit is not used if RWCEN = 0. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 383: Debug Fifo Extended Information Register (Dbg_Fx)

    Bit16 This bit is the most significant bit of the 17-bit core address. 19.3.13 Debug Control Register (DBG_C) Address: 3010h base + Ch offset = 301Ch Read DBGEN BRKEN LOOP1 Write Reset MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 384: Debug Trigger Register (Dbg_T)

    In the case of an end- trace to reset where DBGEN=1 and BEGIN=0, the ARM and BRKEN bits are cleared but the remaining control bits in this register do not change after reset. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 385 0011 Event only B. 0100 A then event only B. 0101 A and B (full mode). 0110 A and not B (full mode). 0111 Inside range. 1000 Outside range. 1001-1111 No trigger. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 386: Debug Status Register (Dbg_S)

    The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill. While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. Debugger not armed. Debugger armed. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 387: Debug Count Status Register (Dbg_Cnt)

    0001 1 word valid. 0010 2 words valid. 0011 3 words valid. 0100 4 words valid. 0101 5 words valid. 0110 6 words valid. 0111 7 words valid. 1000 8 words valid. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 388: Functional Description

    FIFO buffer. In loop1 capture mode, comparator C is not available for use as a normal hardware breakpoint. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 389: Breakpoints

    DBG_C[TAG] affect all three comparators. When DBG_C[BRKEN] = 0, no CPU breakpoints are enabled. When DBG_C[BRKEN] = 1, CPU breakpoints are enabled and the DBG_C[TAG] bit determines whether the breakpoints will be tag-type or force-type MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 390: Trigger Selection

    CPU break will be a tag-type or force-type breakpoint. When DBG_T[TRGSEL] is set, the R/W qualified comparator match signal also passes through the opcode tracking logic. If/when it propagates through this logic, it will cause a MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 391: Begin- And End-Trigger

    DBG_C[ARM] is written to zero or when the DBG_C[DBGEN] bit is low. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 392: Trigger Modes

    B is compared. When the match condition for A or B is met, the corresponding flag in the DBG_S register is set. The A then event only B trigger mode is considered a begin-trigger type and the DBG_T[BEGIN] bit is ignored. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 393 19.4.4.3.9 Outside range, address < A or address > B In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in the DBGS register is set. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 394 Start FIFO at trigger address, force CPU breakpoint when FIFO full Start FIFO at trigger opcode (No CPU breakpoint - keep running) Start FIFO at trigger opcode, force CPU breakpoint when FIFO full MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 395: Fifo

    DBG_C[ARM] and DBG_S[ARMF] will be cleared and no more data will be stored. In non-event only end-trigger modes, if the trigger is at a change of flow address the trigger event will be stored in the FIFO. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 396: Interrupt Priority

    When DBG_T[TRGSEL] is clear and the DBG module is armed to trigger on begin- trigger types, the trigger event is detected on a program fetch of the target address, even when an interrupt becomes pending on the same cycle. In this scenario, the FIFO captures MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...

  • Page 397: Resets

    16-bit CPU address 0xFFFE appears during the reset vector fetch • DBG_C = 0xC0 to enable and arm the DBG module • DBG_T = 0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger mode MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 398 Resets MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 399 Appendix A Changes between revision 5 and 4 Table A-1. Changes between revision 5 and 4 Chapter Description Through out the book • Added a new package of 8-pin DFN. MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 400 MC9S08PA4 Reference Manual, Rev. 5, 08/2017 NXP Semiconductors...
  • Page 401 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based nxp.com on the information in this document.

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