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Introduction
• FIFO for storing change of flow information and event only data
• Source address of conditional branches taken
• Destination address of indirect JMP and JSR instruction
• Destination address of interrupts, RTI, and RTS instruction
• Data associated with Event B trigger modes
• Ability to End-trace until reset and begin-trace from reset
28.1.2 Modes of operation
The on-chip ICE system can be enabled in all MCU functional modes. The DBG module
is disabled if the MCU is secure. The DBG module comparators are disabled when
executing a Background Debug Mode (BDM) command.
28.1.3 Block diagram
The following figure shows the structure of the DBG module.
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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