Clock Stretching - NXP Semiconductors MC9S08SU16 Reference Manual

21.5.1.9 Clock stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of
a transfer. After the master drives SCL low, a slave can drive SCL low for the required
period and then release it. If the slave's SCL low period is greater than the master's SCL
low period, the resulting SCL bus signal's low period is stretched. In other words, the
SCL bus signal's low period is increased to be the same length as the slave's SCL low
period.
21.5.1.10 I2C divider and hold values
For some cases on some devices, the SCL divider value may
vary by ±2 or ±4 when ICR's value ranges from 00h to 0Fh.
These potentially varying SCL divider values are highlighted in
the following table. For the actual SCL divider values for your
device, see the chip-specific details about the I2C module.
ICR SCL SDA hold
divider
(hex)
00 20
01 22
02 24
03 26
04 28
05 30
06 34
07 40
08 28
09 32
0A 36
0B 40
0C 44
0D 48
0E 56
0F 68
10 48
11 56
12 64
13 72
NXP Semiconductors
Table 21-3. I2C divider and hold values
SCL hold SCL hold
value (start) (stop)
value value
7 6 11
7 7 12
8 8 13
8 9 14
9 10 15
9 11 16
10 13 18
10 16 21
7 10 15
7 12 17
9 14 19
9 16 21
11 18 23
11 20 25
13 24 29
13 30 35
9 18 25
9 22 29
13 26 33
13 30 37
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
NOTE
ICR SCL
divider
(hex)
(clocks)
20 160
21 192
22 224
23 256
24 288
25 320
26 384
27 480
28 320
29 384
2A 448
2B 512
2C 576
2D 640
2E 768
2F 960
30 640
31 768
32 896
33 1024
SDA hold SCL hold SCL hold
(clocks) (start) (stop)
value value
17 78
17 94
33 110 113
33 126 129
49 142 145
49 158 161
65 190 193
65 238 241
33 158 161
33 190 193
65 222 225
65 254 257
97 286 289
97 318 321
129 382 385
129 478 481
65 318 321
65 382 385
129 446 449
129 510 513
81
97
381