I2C Status Register (I2C_S) - NXP Semiconductors MC9S08SU16 Reference Manual

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Memory map/register definition

21.4.4 I2C Status register (I2C_S)

Address: 18B0h base + 3h offset = 18B3h
Bit
7
Read
TCF
Write
Reset
1
Field
7
Transfer Complete Flag
TCF
Acknowledges a byte transfer; TCF is set on the completion of a byte transfer. This bit is valid only during
or immediately following a transfer to or from the I2C module. TCF is cleared by reading the I2C data
register in receive mode or by writing to the I2C data register in transmit mode.
NOTE: In the buffer mode, TCF is cleared automatically by internal reading or writing the data register
0
Transfer in progress
1
Transfer complete
6
Addressed As A Slave
IAAS
This bit is set by one of the following conditions:
• The calling address matches the programmed primary slave address in the A1 register, or matches
the range address in the RA register (which must be set to a nonzero value and under the condition
I2C_C2[RMEN] = 1).
• C2[GCAEN] is set and a general call is received.
• SMB[SIICAEN] is set and the calling address matches the second programmed slave address.
• ALERTEN is set and an SMBus alert response address is received
• RMEN is set and an address is received that is within the range between the values of the A1 and
RA registers.
IAAS sets before the ACK bit. The CPU must check the SRW bit and set TX/RX accordingly. Writing the
C1 register with any value clears this bit.
0
Not addressed
1
Addressed as a slave
5
Bus Busy
BUSY
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is
detected and cleared when a STOP signal is detected.
0
Bus is idle
1
Bus is busy
4
Arbitration Lost
ARBL
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing 1 to it.
368
6
5
BUSY
IAAS
0
0
I2C_S field descriptions
I2C_D, with no need waiting for manually reading/writing the I2C data register in Rx/Tx mode.
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
ARBL
RAM
w1c
0
0
Description
2
1
SRW
IICIF
RXAK
w1c
0
0
NXP Semiconductors
0
0

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