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Chapter 4
Interrupt
4.1 Interrupts
Interrupts save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so that processing resumes where it left off before
the interrupt. Other than the software interrupt (SWI), which is a program instruction,
interrupts are caused by hardware events such as an edge on the IRQ pin or a timer-
overflow event. The debug module can also generate an SWI under certain
circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will
be set. The CPU does not respond unless only the local interrupt enable is a logic 1. The
CCR
[I] is 0 to allow interrupts. The
(prevents) all maskable interrupt sources. The user program initializes the stack pointer
and performs other system setups before clearing the
respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction
before responding to the interrupt. The interrupt sequence obeys the same cycle-by-cycle
sequence as the SWI instruction and consists of:
• Saving the CPU registers on the stack.
• Setting the
CCR
• Fetching the interrupt vector for the highest-priority interrupt that is currently
pending.
• Filling the instruction queue with the first three bytes of program information starting
from the address fetched from the interrupt vector locations.
While the CPU is responding to the interrupt, the
another interrupt from interrupting the ISR itself, which is called nesting of interrupts.
Normally, the
CCR
NXP Semiconductors
CCR
[I] to mask further interrupts.
[I] is restored to 0 when the CCR is restored from the value stacked
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
[I] is initially set after reset that masks
CCR
[I] to allow the CPU to
CCR
[I] is automatically set to prevent
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