Phcmp0 Filter Period Register (Gdu_Phcmp0Fpr) - NXP Semiconductors MC9S08SU16 Reference Manual

25.6.3 PHCMP0 Filter Period Register (GDU_PHCMP0FPR)

Address: 20h base + 2h offset = 22h
Bit 7
Read
Write
Reset 0
Field
FILT_PER Filter Sample Period
When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency
details appear in the Functional Description.
This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used to
determine the sampling period.
25.6.4 PHCMP0 Status and Control Register (GDU_PHCMP0SCR)
Address: 20h base + 3h offset = 23h
Bit 7
Read 0
Write
Reset
0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Comparator Interrupt Enable Rising
IER
The IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
3 Comparator Interrupt Enable Falling
IEF
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
NXP Semiconductors
6 5
0 0
GDU_PHCMP0FPR field descriptions
6 5
0
IER
0 0
GDU_PHCMP0SCR field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
FILT_PER
0 0
Description
4 3
CFR
IEF
w1c
0 0
Description
Chapter 25 Gate Drive Unit (GDU)
2 1
0 0
2 1
CFF COUT
w1c
0 0
0
0
0
0
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