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The need for digital filtering and the amount of filtering is dependent on user
requirements. Filtering can become more useful in the absence of an external hysteresis
circuit. Without external hysteresis, high frequency oscillations can be generated at
COUTA when the selected INM and INP input voltages differ by less than the offset
voltage of the differential comparator.
25.7.4.6.1 Enabling filter modes
Filter Modes are enabled by setting CR0[FILTER_CNT] greater than 0x01 and (setting
FPR[FILT_PER] to a non-zero value OR setting CR1[SE]=1). If using the divided bus
clock to drive the filter, it will take samples of COUTA every FPR[FILT_PER] bus clock
cycles.
The filter output will be at logic zero when first initalized, and will subsequently change
when CR0[FILTER_CNT] consecutive samples all agree that the output value has
changed. Said another way, SCR[COUT] will be zero for some initial period, even when
COUTA is at logic one.
Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates
switching current associated with the filtering process.
Always switch to this setting prior to making any changes in
filter parameters. This resets the filter to a known state.
Switching CR0[FILTER_CNT] on the fly without this
intermediate step can result in unexpected behavior.
If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the
sample input. The output state of the filter changes when CR0[FILTER_CNT]
consecutive samples all agree that the output value has changed.
25.7.4.6.2 Latency issues
The FPR[FILT_PER] value (or SAMPLE period) must be set such that the sampling
period is just larger than the period of the expected noise. This way a noise spike will
only corrupt one sample. The CR0[FILTER_CNT] value should be chosen to reduce the
probability of noisy samples causing an incorrect transition to be recognized. The
probability of an incorrect transition is defined as the probability of an incorrect sample
raised to the CR0[FILTER_CNT] power.
The following table summarizes maximum latency values for the various modes of
operation in the absence of noise. Filtering latency is restarted each time an actual output
transition is masked by noise.
NXP Semiconductors
Note
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 25 Gate Drive Unit (GDU)
479
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