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Register addresses assignments
Table 3-2. Peripheral registers availability (continued)
Address
Bytes
0x0060—0x0067
0x0068—0x006E
0x006F—0x006F
0x0070—0x007A
11
0x007B—0x007B
0x007C—0x007E
0x007F—0x007F
0x1800—0x180F
16
0x1810—0x1817
0x1818—0x181F
0x1820—0x1829
10
0x182A—0x182F
48
Peripheral
8
PDB
CMP_CR0, CMP_CR1, CMP_FPR,
8
CMP
―
1
FTM0
―
1
3
KBI
1
IRQ
High Page Registers
SIM_SRS, SIM_SBDFR, SIM_SDIDH,
SIM
8
SIM register filer
―
8
PWM
―
6
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Peripheral registers
PWM_OUTL, PWM_OUTH,
PWM_CNTRL, PWM_CNTRH,
PWM_CMODL, PWM_CMODH,
PWM_VAL0L, PWM_VAL0H,
PWM_VAL1L, PWM_VAL1H,
PWM_VAL2L, PWM_VAL2H,
PWM_VAL3L, PWM_VAL3H,
PWM_VAL4L, PWM_VAL4H,
PWM_VAL5L, PWM_VAL5H,
PWM_DTIM0L, PWM_DTIM0H ,
PWM_DTIM1L, PWM_DTIM1H,
PWM_DMAP1H, PWM_DMAP1L,
PWM_DMAP2H,PWM_DMAP2L
PDB_CTRL0, PDB_CTRL1,
PDB_CMPL0, PDB_CMPH0,
PDB_CNT0,
PDB_CMPL1, PDB_CMPH1,
PDB_CNT1
CMP_SCR, CMP_DACCR,
CMP_MUXCR, CMP_MUXPE
Reserved
FTM0_SC, FTM0_CNTH,
FTM0_CNTL, FTM0_MODH,
FTM0_MODL, FTM0_C0SC,
FTM0_C0VH, FTM0_C0VL,
FTM0_C1SC, FTM0_C1VH,
FTM0_C1VL
Reserved
KBI_SC, KBI_PE, KBI_ES
IRQ_SC
SIM_SDIDL, SIM_SOPT1,
SIM_SOPT2, SIM_MUXPTAL,
SIM_MUXPTAH, SIM_MUXPTBL,
SIM_MUXPTBH, SIM_MUXPTCL,
SIM_SCGC1, SIM_SCGC2,
SIM_SCGC3, SIM_SCDIV
SIM_PORREG0, SIM_PORREG1,
SIM_PORREG2, SIM_PORREG3,
SIM_PORREG4, SIM_PORREG5,
SIM_PORREG6, SIM_PORREG7
Reserved
PWM_CNFGL, PWM_CNFGH,
PWM_CCTRLL, PWM_CCTRLH,
PWM_PECTRLL,
PWM_CINVH
Reserved
Comment
Control bit in PDB_CTRL
decides read counter high or
low
―
―
―
―
Port A KBI
IRQ from Xbar
―
―
―
―
―
NXP Semiconductors
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