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Memory map and register definition
8.5.10 Port B High Drive Strength Selection Register (PORT_PTBHD)
Output extreme high drive strength sink/source current can be enabled by setting the
corresponding bit in the PORT_PTBHD register for PTB7. Output extremely high sink/
source current is enabled when they are operated as output. Extreme high drive function
is disabled if the pin is configured as an input by the parallel I/O control logic. When
configured as any shared peripheral function, extreme high drive function still works on
these pins, but only when they are configured as outputs.
Address: 0h base + 18E6h offset = 18E6h
Bit
7
Read
HD7
Write
Reset
0
Field
7
Output High Drive Strength Selection for Port B Bit 7
HD7
This bit enables the extreme high drive capability of associated PTB pin.
0
Low output drive enabled for port B bit 7.
1
High output drive enabled for port B bit 7.
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8.5.11 Port Clock Division Register (PORT_FCLKDIV)
Configure the high/low level glitch width threshold. Glitches that are shorter than the
selected clock width will be filtered out; glitches that are more than twice the selected
clock width will not be filtered out (they will pass to the internal circuitry).
Address: 0h base + 18ECh offset = 18ECh
Bit
7
Read
Write
Reset
0
Field
7–5
Filter Division Set 3
FLTDIV3
92
6
5
0
0
PORT_PTBHD field descriptions
6
5
FLTDIV3
0
0
PORT_FCLKDIV field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
0
0
0
Description
4
3
FLTDIV2
0
0
Description
2
1
0
0
2
1
FLTDIV1
0
0
NXP Semiconductors
0
0
0
0
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