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Memory map and register definition
9.8 Memory map and register definition
The SIM module contains many fields for selecting the clock source and dividers for
various module clocks.
Absolute
address
(hex)
1800
System Reset Status Register (SIM_SRS)
System Background Debug Force Reset Register
1801
(SIM_SBDFR)
1802
System Device Identification Register: High (SIM_SDIDH)
1803
System Device Identification Register: Low (SIM_SDIDL)
1804
System Options Register 1 (SIM_SOPT1)
1805
System Options Register 2 (SIM_SOPT2)
System Port A Pin Multiplexing Control Register: Low
1806
(SIM_MUXPTAL)
System Port A Pin Multiplexing Control Register: High
1807
(SIM_MUXPTAH)
System Port B Pin Multiplexing Control Register: Low
1808
(SIM_MUXPTBL)
System Port B Pin Multiplexing Control Register: High
1809
(SIM_MUXPTBH)
System Port C Pin Multiplexing Control Register: Low
180A
(SIM_MUXPTCL)
180C
System Clock Gating Control 1 Register (SIM_SCGC1)
180D
System Clock Gating Control 2 Register (SIM_SCGC2)
180E
System Clock Gating Control 3 Register (SIM_SCGC3)
180F
System Clock Divider Register (SIM_SCDIV)
1810
System POR Register (SIM_PORREG0)
1811
System POR Register (SIM_PORREG1)
1812
System POR Register (SIM_PORREG2)
1813
System POR Register (SIM_PORREG3)
1814
System POR Register (SIM_PORREG4)
1815
System POR Register (SIM_PORREG5)
1816
System POR Register (SIM_PORREG6)
1817
System POR Register (SIM_PORREG7)
1880
Illegal Address Register: High (SIM_ILLAH)
1881
Illegal Address Register: Low (SIM_ILLAL)
18F8
Universally Unique Identifier Register 0 (SIM_UUID0)
104
SIM memory map
Register name
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
Reset value
(in bits)
8
R
82h
W
8
(always
00h
reads 0)
8
R
00h
8
R
45h
8
R/W
C0h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
30h
8
R/W
00h
8
R/W
00h
8
R/W
20h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R
Undefined
8
R
Undefined
8
R
Undefined
NXP Semiconductors
Section/
page
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