Receiver Wake-Up Operation - NXP Semiconductors MC9S08SU16 Reference Manual

Functional description
In the case of a framing error, provided the received character was not a break character,
the sampling logic that searches for a falling edge is filled with three logic 1 samples so
that a new start bit can be detected almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters
until the framing error flag is cleared. The receive shift register continues to function, but
a complete character cannot transfer to the receive data buffer if SCI_S1[FE] remains set.

22.5.3.2 Receiver wake-up operation

Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the
characters in a message intended for a different SCI receiver. In such a system, all
receivers evaluate the first character(s) of each message, and as soon as they determine
the message is intended for a different receiver, they write logic 1 to the receiver wake up
control field (SCI_C2[RWU]). When SCI_C2[RWU] is set, the status flags associated
with the receiver, (with the exception of the idle bit, IDLE, when SCI_S2[RWUID] is
set), are inhibited from setting, thus eliminating the software overhead for handling the
unimportant message characters. At the end of a message, or at the beginning of the next
message, all receivers automatically force SCI_C2[RWU] to 0, so all receivers wake up
in time to look at the first character(s) of the next message.
22.5.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
SCI_C2[RWU] is cleared automatically when the receiver detects a full character time of
the idle-line level. The SCI_C1[M] control field selects 8-bit or 9-bit data mode and
SCI_BDH[SBNS] selects 1-bit or 2-bit stop bit number that determines how many bit
times of idle are needed to constitute a full character time, 10 or 11 or 12 bit times
because of the start and stop bits.
When SCII_C2[RWU] is 1 and SCI_S2[RWUID] is 0, the idle condition that wakes up
the receiver does not set SCI_S1[IDLE]. The receiver wakes up and waits for the first
data character of the next message that sets SCI_S1[RDRF] and generates an interrupt, if
enabled. When SCI_S2[RWUID] is 1, any idle condition sets SCI_S1[IDLE] flag and
generates an interrupt if enabled, regardless of whether SCI_C2[RWU] is 0 or 1.
The idle-line type (SCI_C1[ILT]) control bit selects one of two ways to detect an idle
line. When SCI_C1[ILT] is cleared, the idle bit counter starts after the start bit so the stop
bit and any logic 1s at the end of a character count toward the full character time of idle.
When SCI_C1[ILT] is set, the idle bit counter does not start until after a stop bit time, so
the idle detection is not affected by the data in the last character of the previous message.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
414 NXP Semiconductors