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Memory Map and Register Descriptions
26.4.18 PWM Disable Mapping Registers 1: High (PWM_DMAP1H)
These write-protectable registers determine which PWM pins are affected by the fault
protection inputs. Reset sets all of the bits used in the PWM disable mapping registers.
These registers are write protected after the WP bit in the PWM configure register is set.
Reserved bits 15-8 in the DMAP2 register cannot be modified. The bits are read as zero.
Address: 40h base + 1Dh offset = 5Dh
Bit
7
Read
Write
Reset
1
Field
DISMAP15_8
PWM Disable Mapping 15:8
26.4.19 PWM Disable Mapping Registers 2: Low (PWM_DMAP2L)
These write-protectable registers determine which PWM pins are affected by the fault
protection inputs. Reset sets all of the bits used in the PWM disable mapping registers.
These registers are write protected after the WP bit in the PWM configure register is set.
Reserved bits 15-8 in the DMAP2 register cannot be modified. The bits are read as zero.
Address: 40h base + 1Eh offset = 5Eh
Bit
7
Read
Write
Reset
1
Field
DISMAP23_16
PWM Disable Mapping 23:16
26.4.20 PWM Configure Register: Low (PWM_CNFGL)
Address: 40h base + 17E0h offset = 1820h
Bit
7
Read
0
Write
Reset
0
520
6
5
1
1
PWM_DMAP1H field descriptions
6
5
1
1
PWM_DMAP2L field descriptions
6
5
BOTNEG
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
DISMAP15_8
1
1
Description
4
3
DISMAP23_16
1
1
Description
4
3
INDEP
0
0
2
1
1
1
2
1
1
1
2
1
WP
0
0
NXP Semiconductors
0
1
0
1
0
0
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