Pdb1 Comparison Low Register (Pdb_Cmpl1) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
7–1 PDB0 counter value [7:1]
CNT0_7_1
Control bit [CNTSEL] decides read counter high or low.
0 PDB0 Counter Value 0 and Module Enable
CNT0_0_
This bit read as counter value 0 and is also used to enable the PDB module 0, the writing operation
PDBEN0
doesn't take effect the counter's value. Writing 0 to bit0 of this register: Counter is off and Trigger output is
low.
Writing 1 to bit0 of this register: Counter is enabled.

23.6.6 PDB1 Comparison Low Register (PDB_CMPL1)

The Comparison registers contain the high and low bytes of the comparison value for the
counter. After the counter reaches the comparison value, the timer comparison flag
(TCF0) becomes set at the next clock.
Writing to the CMPx1 registers would take effect immediately.
Address: 60h base + 5h offset = 65h
Bit 7
Read
Write
Reset
1
Field
CMPL1 PDB1 low byte of the comparison value
23.6.7 PDB1 Comparison High Register (PDB_CMPH1)
The Comparison registers contain the high and low bytes of the comparison value for the
counter. After the counter reaches the comparison value, the timer comparison flag
(TCF0) becomes set at the next clock.
Writing to the CMPx1 registers would take effect immediately.
Address: 60h base + 6h offset = 66h
Bit 7
Read
Write
Reset 1
NXP Semiconductors
PDB_CNT0 field descriptions
NOTE
6 5
1 1
PDB_CMPL1 field descriptions
NOTE
6 5
1 1
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 23 Programmable Delay Block (PDB)
Description
4 3
CMPL1
1 1
Description
4 3
CMPH1
1 1
2 1
1 1
2 1
1 1
0
1
0
1
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