NXP Semiconductors MC9S12G 16-bit Manuals

Manuals and User Guides for NXP Semiconductors MC9S12G 16-bit. We have 1 NXP Semiconductors MC9S12G 16-bit manual available for free PDF download: Reference Manual

NXP Semiconductors MC9S12G Reference Manual (1277 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 5 MB

Device Overview Mc9S12G-Family

7
- Table of Contents
  7
Table of Contents

22
- Chapter 1 Device Overview MC9S12G-Family
  
  27
  - Features
    28
  - Chip-Level Features
    30
    
    S12 16-Bit Central Processor Unit (CPU)
    31
    
    Main External Oscillator (XOSCLCP)
    32
    
    System Integrity Support
    33
    
    Serial Communication Interface Module (SCI)
    34
    
    Reference Voltage Attenuator (RVA)
    35
  - Key Performance Parameters
    36
  - Family Memory Map
    37
    
    Part ID Assignments
    42
  - Ps3
    37
  - Signal Description and Device Pinouts
    43
    
    Detailed Signal Descriptions
    44
    
    Power Supply Pins
    48
  - Device Pinouts
    51
  - Pm0
    54
    
    S12GNA16 and S12GNA32
    58
    
    S12Gn48
    60
  - Ps4
    54
  - Ps5
    54
  - Ps6
    54
  - Ps7
    54
  - Pm2
    69
  - Pm3
    69
  - The Regular I/O Characteristics
    69
    
    S12G48 and S12G64
    70
  - Miso0
    78
  - Mosi0
    79
    
    S12GA48 and S12GA64
    80
    
    S12G96 and S12G128
    87
  - Api_Extc
    95
    
    S12GA96 and S12GA128
    99
    
    S12G192 and S12G240
    111
    
    S12GA192 and S12GA240
    123
1.9 System Clock Description

138
- System Clock Description
  138
  - Chip Configuration Summary
    139
  - Interrupt Vectors
    140
  - Effects of Reset
    142
- Autonomous Clock (ACLK) Configuration
  143
- ADC Result Reference
  144
- BDM Clock Source Connectivity
  145
- Chapter 2 Port Integration Module (S12GPIMV1)
  
  147
  - Overview
    148
  - Block Diagram
    149
  - Package Code
    150
  - PIM Routing - Functional Description
    152
    
    Pin BKGD
    161
    
    Pins PD7-0
    163
    
    Pins PS7-0
    165
    
    Pins PM3-0
    167
    
    Pins PJ7-0
    169
    
    Pins AD15-0
    170
  - PIM Ports - Memory Map and Register Definition
    176
    
    Register Map
    179
    
    Register Descriptions
    194
  - PIM Ports - Functional Description
    239
    
    Pin Configuration Summary
    241
    
    Interrupts
    242
    
    Initialization/Application Information
    244
    
    Emulation of Smaller Packages
    245
- Chapter 3 5V Analog Comparator (ACMPV1)
  
  247
  - External Signals
    248
  - Memory Map and Register Definition
    249
  - Functional Description
    251
- Chapter 4 Reference Voltage Attenuator (RVAV1)
  
  253
  - External Signals
    254
  - Memory Map and Register Definition
    255
  - Functional Description
    256
- Chapter 5 S12G Memory Map Controller (S12GMMCV1)
  
  257
  - Features
    258
    
    External Signal Description
    259
    
    Register Descriptions
    260
    
    Functional Description
    264
  - Unimplemented and Reserved Address Ranges
    268
  - Prioritization of Memory Accesses
    269
- Chapter 6 Interrupt Module (S12SINTV1)
  
  271
  - Modes of Operation
    272
  - External Signal Description
    273
  - Functional Description
    274
  - Reset Exception Requests
    275
  - Initialization/Application Information
    276
- Chapter 7 Background Debug Module (S12SBDMV1)
  
  279
  - Modes of Operation
    280
  - Block Diagram
    281
  - Register Descriptions
    282
  - Family ID Assignment
    285
  - Security
    286
  - BDM Hardware Commands
    287
  - Standard BDM Firmware Commands
    288
  - BDM Command Structure
    289
  - BDM Serial Interface
    291
  - Serial Interface Hardware Handshake Protocol
    294
  - Hardware Handshake Abort Procedure
    296
  - SYNC — Request Timed Reference Pulse
    299
  - Serial Communication Time out
    300
- Chapter 8 S12S Debug Module (S12SDBGV2)
  
  303
  - Overview
    304
  - Modes of Operation
    305
  - External Signal Description
    306
  - Register Descriptions
    307
  - Functional Description
    322
  - S12SDBG Operation
    323
  - Match Modes (Forced or Tagged)
    327
  - State Sequence Control
    328
  - Trace Buffer Operation
    329
  - Tagging
    336
  - Application Information
    338
  - Scenario 2
    339
  - Scenario 5
    341
  - Scenario 8
    342
- Chapter 9 Security (S12XS9SECV2)
  
  345
- Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)
  
  351
  - Features
    352
  - Modes of Operation
    353
  - S12CPMU Block Diagram
    356
    
    Signal Description
    357
    
    VDDR — Regulator Power Input Pin
    358
    
    VDD — Internal Regulator Output Supply (Core Logic)
    359
    
    Register Descriptions
    361
    
    Functional Description
    387
  - Startup from Reset
    388
  - Stop Mode Using PLLCLK as Bus Clock
    389
  - External Oscillator
    390
  - System Clock Configurations
    391
  - Resets
    393
  - Power-On Reset (POR)
    395
    
    Interrupts
    396
    
    Initialization/Application Information
    398
- Chapter 11 Analog-To-Digital Converter (ADC10B8CV2)
  
  403
  - Features
    404
  - Modes of Operation
    405
  - Block Diagram
    406
  - Signal Description
    407
  - Register Descriptions
    409
  - Functional Description
    424
  - Resets
    426
- Chapter 12 Analog-To-Digital Converter (ADC12B8CV2)
  
  427
  - Features
    428
  - Modes of Operation
    429
  - Block Diagram
    430
  - Signal Description
    431
  - Register Descriptions
    433
  - Functional Description
    449
  - Resets
    451
- Chapter 13 Analog-To-Digital Converter (ADC10B12CV2)
  
  453
  - Introduction
    454
    
    Modes of Operation
    455
    
    Block Diagram
    456
  - Signal Description
    457
    
    Register Descriptions
    460
    
    Functional Description
    475
    
    Resets
    477
- Chapter 14 Analog-To-Digital Converter (ADC12B12CV2)
  
  479
  - Introduction
    480
    
    Modes of Operation
    481
    
    Block Diagram
    482
    
    Signal Description
    483
    
    Register Descriptions
    486
    
    Functional Description
    502
    
    Resets
    504
- Chapter 15 Analog-To-Digital Converter (ADC10B16CV2)
  
  505
  - Introduction
    506
    
    Modes of Operation
    507
    
    Block Diagram
    508
    
    Signal Description
    509
    
    Register Descriptions
    512
    
    Functional Description
    527
    
    Resets
    529
- Chapter 16 Analog-To-Digital Converter (ADC12B16CV2)
  
  531
  - Introduction
    532
  - Modes of Operation
    533
  - Block Diagram
    534
  - Signal Description
    535
  - Register Descriptions
    538
  - Functional Description
    554
  - Resets
    556
- Chapter 17 Digital Analog Converter (DAC_8B5V)
  
  557
  - Features
    558
  - Block Diagram
    559
  - AMPM Input Pin
    560
    
    Register Descriptions
    561
    
    Functional Description
    562
  - Mode "Off
    563
  - Mode "Unbuffered DAC
    564
- Chapter 18 Scalable Controller Area Network (S12MSCANV3)
  
  567
  - Glossary
    568
  - Features
    569
  - TXCAN — CAN Transmitter Output Pin
    570
  - Register Descriptions
    572
  - Programmer's Model of Message Storage
    591
  - Functional Description
    601
  - Message Storage
    602
  - Identifier Acceptance Filter
    605
  - Modes of Operation
    611
    
    Low-Power Options
    613
    
    Reset Initialization
    617
  - Initialization/Application Information
    619
- Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2)
  
  621
  - Block Diagram
    622
  - Memory Map and Register Definition
    623
    
    Functional Description
    638
    
    PWM Channel Timers
    641
  - Resets
    648
  - Interrupts
    649
- Chapter 20 Serial Communication Interface (S12SCIV5)
  
  651
  - Features
    652
    
    Block Diagram
    653
    
    Module Memory Map and Register Definition
    654
    
    Functional Description
    665
    
    Infrared Interface Submodule
    666
    
    LIN Support
    667
    
    Baud Rate Generation
    669
    
    Transmitter
    670
    
    Receiver
    675
    
    Single-Wire Operation
    683
    
    Loop Operation
    684
    
    Interrupt Operation
    685
    
    Recovery from Wait Mode
    687
- Chapter 21 Serial Peripheral Interface (S12SPIV5)
  
  689
  - Modes of Operation
    690
  - External Signal Description
    691
  - MISO — Master In/Slave out Pin
    692
  - Register Descriptions
    693
  - Functional Description
    701
  - Master Mode
    702
  - Slave Mode
    703
  - Transmission Formats
    704
  - MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors
    708
  - SPI Baud Rate Generation
    710
  - Special Features
    711
  - Error Conditions
    712
  - Low Power Mode Options
    713
- Chapter 22 Timer Module (TIM16B6CV3)
  
  717
  - Modes of Operation
    718
    
    External Signal Description
    719
    
    Functional Description
    731
    
    Prescaler
    732
    
    Input Capture
    733
  - Resets
    734
- Chapter 23 Timer Module (TIM16B8CV3)
  
  735
  - Modes of Operation
    736
  - External Signal Description
    739
  - Register Descriptions
    740
  - Functional Description
    756
    
    Prescaler
    758
    
    Pulse Accumulator
    759
    
    Event Counter Mode
    760
    
    Channel [7:0] Interrupt (C[7:0]F)
    761
    
    Glossary
    764
    
    Block Diagram
    765
- Chapter 24 16 Kbyte Flash Module (S12FTMRG16K1V1)
  
  763
  - External Signal Description
    766
  - Memory Map and Registers
    767
    
    Register Descriptions
    770
  - Functional Description
    787
    
    Allowed Simultaneous P-Flash and EEPROM Operations
    792
    
    Flash Command Description
    793
    
    Interrupts
    807
    
    Wait Mode
    808
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    809
    
    Mode and Security Effects on Flash Command Availability
    810
- Chapter 25 32 Kbyte Flash Module (S12FTMRG32K1V1)
  
  811
  - Glossary
    812
  - Block Diagram
    813
  - External Signal Description
    814
  - Memory Map and Registers
    815
    
    Register Descriptions
    818
    
    Functional Description
    837
    
    Internal NVM Resource (NVMRES)
    838
    
    MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors
    839
    
    Allowed Simultaneous P-Flash and EEPROM Operations
    843
    
    Flash Command Description
    844
    
    Interrupts
    858
    
    Wait Mode
    859
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    860
    
    Mode and Security Effects on Flash Command Availability
    861
- Chapter 26 48 Kbyte Flash Module (S12FTMRG48K1V1)
  
  863
  - Glossary
    864
  - Block Diagram
    866
  - Memory Map and Registers
    867
  - Register Descriptions
    871
  - Functional Description
    890
  - Internal NVM Resource (NVMRES)
    891
  - Allowed Simultaneous P-Flash and EEPROM Operations
    896
  - Flash Command Description
    897
  - Interrupts
    911
  - Wait Mode
    912
  - Unsecuring the MCU in Special Single Chip Mode Using BDM
    913
  - Mode and Security Effects on Flash Command Availability
    914
- Chapter 27 64 Kbyte Flash Module (S12FTMRG64K1V1)
  
  915
  - Glossary
    916
  - Block Diagram
    917
    
    External Signal Description
    918
    
    Memory Map and Registers
    919
    
    Register Descriptions
    922
    
    Functional Description
    941
    
    Internal NVM Resource (NVMRES)
    942
    
    Allowed Simultaneous P-Flash and EEPROM Operations
    947
    
    Flash Command Description
    948
    
    Interrupts
    962
    
    Wait Mode
    963
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    964
    
    Mode and Security Effects on Flash Command Availability
    965
- Chapter 28 96 Kbyte Flash Module (S12FTMRG96K1V1)
  
  967
  - Glossary
    968
  - Block Diagram
    969
  - External Signal Description
    970
  - Memory Map and Registers
    971
  - Register Descriptions
    974
  - Functional Description
    993
  - Internal NVM Resource (NVMRES)
    994
  - Allowed Simultaneous P-Flash and EEPROM Operations
    999
  - Flash Command Description
    1000
  - Interrupts
    1014
  - Wait Mode
    1015
  - Unsecuring the MCU in Special Single Chip Mode Using BDM
    1016
  - MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors
    1017
- Chapter 29 128 Kbyte Flash Module (S12FTMRG128K1V1)
  
  1019
  - Glossary
    1020
  - Features
    1021
    
    External Signal Description
    1022
    
    Memory Map and Registers
    1023
    
    Register Descriptions
    1027
    
    Functional Description
    1045
    
    Internal NVM Resource (NVMRES)
    1046
    
    Allowed Simultaneous P-Flash and EEPROM Operations
    1051
    
    Flash Command Description
    1052
    
    Interrupts
    1066
    
    Wait Mode
    1067
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    1068
    
    Mode and Security Effects on Flash Command Availability
    1069
- Chapter 30 192 Kbyte Flash Module (S12FTMRG192K2V1)
  
  1071
  - Glossary
    1072
  - Block Diagram
    1073
  - External Signal Description
    1074
  - Memory Map and Registers
    1075
  - Register Descriptions
    1079
  - Functional Description
    1097
  - Internal NVM Resource (NVMRES)
    1098
  - Allowed Simultaneous P-Flash and EEPROM Operations
    1103
  - Flash Command Description
    1104
  - Interrupts
    1117
  - Wait Mode
    1118
  - Security
    1119
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    1120
- Chapter 31 240 Kbyte Flash Module (S12FTMRG240K2V1)
  
  1123
  - Glossary
    1124
  - Block Diagram
    1125
  - External Signal Description
    1126
  - Memory Map and Registers
    1127
  - Register Descriptions
    1131
  - Functional Description
    1149
  - Internal NVM Resource (NVMRES)
    1150
  - Allowed Simultaneous P-Flash and EEPROM Operations
    1155
  - Flash Command Description
    1156
  - Interrupts
    1169
  - Wait Mode
    1170
  - Security
    1171
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    1172
- Appendix A Electrical Characteristics
  
  1175
  - A.1 General
    1176
    
    A.1.3 Pins
    1177
    
    A.1.6 ESD Protection and Latch-Up Immunity
    1178
    
    A.1.7 Operating Conditions
    1179
    
    A.1.8 Power Dissipation and Thermal Characteristics
    1181
  - A.2 I/O Characteristics
    1185
  - A.3 Supply Currents
    1189
  - A.4 ADC Characteristics
    1194
    
    A.4.2 Factors Influencing Accuracy
    1195
    
    A.4.3 ADC Accuracy
    1196
    
    A.4.4 ADC Temperature Sensor
    1206
  - A.6 DAC Characteristics
    1208
    
    A.7.1 Timing Parameters
    1209
    
    A.7.2 NVM Reliability Parameters
    1214
  - A.8 Phase Locked Loop
    1215
    
    A.8.2 Electrical Characteristics for the PLL
    1217
  - A.10 Electrical Characteristics for the Oscillator (XOSCLCP)
    1219
  - A.11 Reset Characteristics
    1220
  - A.12 Electrical Specification for Voltage Regulator
    1221
  - A.13 Chip Power-Up and Voltage Drops
    1223
  - A.14 Mscan
    1224
  - A.15 SPI Timing
    1225
    
    A.15.2 Slave Mode
    1227
  - A.16 ADC Conversion Result Reference
    1229
- Appendix B Detailed Register Address Map
  
  1231
- Appendix C Ordering and Shipping Information
  
  1251
- Appendix D Package and die Information
  
  1253
  - D.1 100 LQFP Mechanical Dimensions
    1254
  - D.2 64 LQFP Mechanical Dimensions
    1257
  - D.3 48 LQFP Mechanical Dimensions
    1260
  - D.4 48 QFN Mechanical Dimensions
    1262
  - D.5 32 LQFP Mechanical Dimensions
    1265
  - D.6 20 TSSOP Mechanical Dimensions
    1268
  - D.7 KGD Information
    1271

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NXP Semiconductors MC9S12G 16-bit Manuals

NXP Semiconductors MC9S12G Reference Manual (1277 pages)

Table of Contents

Device Overview Mc9S12G-Family

Table of Contents

Chapter 1 Device Overview MC9S12G-Family

1.9 System Clock Description

Chapter 2 Port Integration Module (S12GPIMV1)

Chapter 3 5V Analog Comparator (ACMPV1)

Chapter 4 Reference Voltage Attenuator (RVAV1)

Chapter 5 S12G Memory Map Controller (S12GMMCV1)

Chapter 6 Interrupt Module (S12SINTV1)

Chapter 7 Background Debug Module (S12SBDMV1)

Chapter 8 S12S Debug Module (S12SDBGV2)

Chapter 9 Security (S12XS9SECV2)

Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)

Chapter 11 Analog-To-Digital Converter (ADC10B8CV2)

Chapter 12 Analog-To-Digital Converter (ADC12B8CV2)

Chapter 13 Analog-To-Digital Converter (ADC10B12CV2)

Chapter 14 Analog-To-Digital Converter (ADC12B12CV2)

Chapter 15 Analog-To-Digital Converter (ADC10B16CV2)

Chapter 16 Analog-To-Digital Converter (ADC12B16CV2)

Chapter 17 Digital Analog Converter (DAC_8B5V)

Chapter 18 Scalable Controller Area Network (S12MSCANV3)

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2)

Chapter 20 Serial Communication Interface (S12SCIV5)

Chapter 21 Serial Peripheral Interface (S12SPIV5)

Chapter 22 Timer Module (TIM16B6CV3)

Chapter 23 Timer Module (TIM16B8CV3)

Chapter 24 16 Kbyte Flash Module (S12FTMRG16K1V1)

Chapter 25 32 Kbyte Flash Module (S12FTMRG32K1V1)

Chapter 26 48 Kbyte Flash Module (S12FTMRG48K1V1)

Chapter 27 64 Kbyte Flash Module (S12FTMRG64K1V1)

Chapter 28 96 Kbyte Flash Module (S12FTMRG96K1V1)

Chapter 29 128 Kbyte Flash Module (S12FTMRG128K1V1)

Chapter 30 192 Kbyte Flash Module (S12FTMRG192K2V1)

Chapter 31 240 Kbyte Flash Module (S12FTMRG240K2V1)

Appendix A Electrical Characteristics

Appendix B Detailed Register Address Map

Appendix C Ordering and Shipping Information

Appendix D Package and die Information

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