Memory Map And Register Descriptions - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions

Fault 1
or Fault 3
PWM half-cycle boundaries occur at both the PWM cycle start
and when the counter equals the modulus, so in edge-aligned
operation full cycles and half cycles are equal.
Fault protection also applies during software output control
when the OUTCTLn bits are set. Fault clearing still occurs at
half PWM cycle boundaries while the PWM generator is
engaged where PWMEN=1. However, the OUTn bits can also
control the PWM pins while the PWM generator is off where
PWMEN=0. Thus, fault clearing occurs at PWM operation
clock cycles while the PWM generator is off and at the start of
PWM cycles when the generator is engaged.
26.4 Memory Map and Register Descriptions
Absolute
address
(hex)
40 PWM Control Register: Low (PWM_CTRLL)
41 PWM Control Register: High (PWM_CTRLH)
42 PWM Fault Control Register: Low (PWM_FCTRLL)
43 PWM Fault Control Register: High (PWM_FCTRLH)
PWM Fault Status Acknowledge Register: Low
44
(PWM_FLTACKL)
PWM Fault Status Acknowledge Register: High
45
(PWM_FLTACKH)
46 PWM Output Control Register: Low (PWM_OUTL)
47 PWM Output Control Register: High (PWM_OUTH)
48 PWM Counter Register: Low (PWM_CNTRL)
504
PWMS Enabled PWMS Disabled
FFLAGn
Cleared
Figure 26-31. Manual fault clearing (example 2)
PWM memory map
Register name
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
PWMS Enabled
NOTE
Width
(in bits)
8
8
8
8
8
8
8
8
8
Section/
Access Reset value
R/W 00h 26.4.1/506
R/W 00h 26.4.2/507
R/W 00h 26.4.3/508
R/W 00h 26.4.4/510
W 00h 26.4.5/510
R 00h 26.4.6/511
R/W 00h 26.4.7/513
R/W 00h 26.4.8/514
R 00h 26.4.9/514
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