Table of Contents
Advertisement
Direct-page registers can be accessed with efficient direct addressing mode instructions.
which requires only the lower byte of the address. Bit manipulation instructions can be
used to access any bit in a direct-page register.
Address
Bytes
0x0000—0x0000
0x0001—0x0001
0x0002—0x0002
0x0003—0x0003
0x0004—0x0004
0x0005—0x0005
0x0006—0x0006
0x0007—0x0007
0x0008—0x000D
0x000E—0x00F
0x0010—0x0017
0x0018—0x001F
0x0020—0x002B
12
0x002C—0x002F
0x0030—0x0037
0x0038—0x003F
0x0040—0x005F
32
NXP Semiconductors
Table 3-2. Peripheral registers availability
Peripheral
Direct Page Registers
1
PTA
1
PTB
1
PTC
1
PTA
1
PTB
1
PTC
1
XBAR
―
1
MTIM_SC, MTIM_CLK, MTIM_CNTH,
6
MTIM
2
IPC
ADC0_SC1, ADC0_SC2, ADC0_SC3,
8
ADC0
ADC0_SC4, ADC0_RH, ADC0_RL,
ADC1_SC1, ADC1_SC2, ADC1_SC3,
8
ADC1
ADC1_SC4, ADC1_RH, ADC1_RL,
GDU
―
4
PWT0_CS, PWT0_CR, PWT0_PPH,
8
PWT0
PWT1_CS, PWT1_CR, PWT1_PPH,
8
PWT1
PWM
PWM_FLTACKL, PWM_FLTACKH,
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Peripheral registers
PORT_PTAD
PORT_PTBD
PORT_PTCD
PORT_PTADD
PORT_PTBDD
PORT_PTCDD
XBAR_EXTMUX
Reserved
MTIM_CNTL, MTIM_MODH,
MTIM_MODL
IPC_SC, IPC_IPMPS
ADC0_CVH, ADC0_CVL
ADC1_CVH, ADC1_CVL
GDU_PHCMP0CR0,
GDU_PHCMP0CR1,
GDU_PHCMP0FPR,
GDU_PHCMP0SCR,
GDU_PHCMP1CR0,
GDU_PHCMP1CR1,
GDU_PHCMP1FPR,
GDU_PHCMP1SCR,
GDU_PHCMP2CR0,
GDU_PHCMP2CR1,
GDU_PHCMP2FPR,
GDU_PHCMP2SCR
Reserved
PWT0_PPL, PWT0_NPH,
PWT0_NPL, PWT0_CNTH,
PWT0_CNTL
PWT1_PPL, PWT1_NPH,
PWT1_NPL, PWT1_CNTH,
PWT1_CNTL
PWM_CTRLL, PWM_CTRLH,
PWM_FCTRLL, PWM_FCTRLH,
Chapter 3 Memory
Comment
Port data
Port data direction
PWM channel 2-to-1 Mux
―
―
―
―
―
―
―
―
―
―
47
Advertisement
Table of Contents
