NXP Semiconductors MC9S08SU16 Reference Manual page 509

Field
0 Manual fault clearing of FAULT3 pin faults.
1 Automatic fault clearing of FAULT3 pin faults.
5 FAULT2 Pin Interrupt Enable
FIE2
This read/write bit enables interrupt requests generated by the filtered FAULT2 pin. A reset clears FIE2.
NOTE: The fault protection circuit is independent of the FIE2 bits and is always active. If a fault is
0 FAULT2 interrupt requests disabled
1 FAULT2 interrupt requests enabled
4 FAULT2 Pin Clearing Mode
FMODE2
This read/write bit selects automatic or manual clearing of FAULT2 pin faults. A reset clears FMODE2.
0 Manual fault clearing of FAULT2 pin faults.
1 Automatic fault clearing of FAULT2 pin faults.
3 FAULT1 Pin Interrupt Enable
FIE1
This read/write bit enables interrupt requests generated by the filtered FAULT1 pin. A reset clears FIE1.
NOTE: The fault protection circuit is independent of the FIE1 bits and is always active. If a fault is
0 FAULT1 interrupt requests disabled
1 FAULT1 interrupt requests enabled
2 FAULT1 Pin Clearing Mode
FMODE1
This read/write bit selects automatic or manual clearing of FAULT1 pin faults. A reset clears FMODE1.
0 Manual fault clearing of FAULT1 pin faults.
1 Automatic fault clearing of FAULT1 pin faults.
1 FAULT0 Pin Interrupt Enable
FIE0
This read/write bit enables interrupt requests generated by the filtered FAULT0 pin. A reset clears FIE0.
NOTE: The fault protection circuit is independent of the FIE0 bits and is always active. If a fault is
0 FAULT0 interrupt requests disabled
1 FAULT0 interrupt requests enabled
0 FAULT0 Pin Clearing Mode
FMODE0
This read/write bit selects automatic or manual clearing of FAULT0 pin faults. A reset clears FMODE0.
0 Manual fault clearing of FAULT0 pin faults.
1 Automatic fault clearing of FAULT0 pin faults.
NXP Semiconductors
PWM_FCTRLL field descriptions (continued)
detected, the PWM pins are disabled according to the PWM disable mapping register.
detected, the PWM pins are disabled according to the PWM disable mapping register.
detected, the PWM pins are disabled according to the PWM disable mapping register.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Description
509