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PWM
Operation Clock
PWMEN
Bit
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PWM
Pins
Figure 26-26. PWMEN and PWM pins in independent operation (OUTCTL0–5 = 0)
PWM
Operation Clock
PWMEN
Bit
PWM
Pins
Figure 26-27. PWMEN and PWM pins in complement operation (OUTCTL0, 2, 4 = 0)
When the PWMEN bit is cleared:
• The PWMn pins will be in their inactive status unless OUTCTLn=1
• The PWM counter is cleared and does not count
• The PWM generator forces its outputs to zero
• The PWMF and pending interrupt requests are not cleared
• All fault circuitry remains active
• Software output control remains active if OUTCTLn=1
• Deadtime insertion continues during software output control
26.3.9 Fault protection
Fault protection can disable any combination of PWM pins. Faults are generated by either
a 1 or 0, determined by the fault polarity control bits in the fault control (FCTRL) register
on any of the FAULT pins. Each FAULT pin can be mapped arbitrarily to any of the
PWM pins. When fault protection hardware disables PWM pins, the PWM generator
continues to run, only the output pins are deactivated. The fault decoder disables PWM
pins selected by the fault logic and the disable mapping register. Please see the following
figure. Each bank of four bits in the disable mapping registers (DMAP1-2) controls the
mapping for a single PWM pin. Please refer to the following table. The fault protection is
enabled even when the PWM is not enabled; therefore, if a fault is latched in, it must be
cleared prior to enabling the PWM to prevent an unexpected interrupt.
NXP Semiconductors
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
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