System Reset Status Register (Sim_Srs) - NXP Semiconductors MC9S08SU16 Reference Manual

Absolute
address
(hex)
18F9 Universally Unique Identifier Register 1 (SIM_UUID1)
18FA Universally Unique Identifier Register 2 (SIM_UUID2)
18FB Universally Unique Identifier Register 3 (SIM_UUID3)
18FC Universally Unique Identifier Register 4 (SIM_UUID4)
18FD Universally Unique Identifier Register 5 (SIM_UUID5)
18FE Universally Unique Identifier Register 6 (SIM_UUID6)
18FF Universally Unique Identifier Register 7 (SIM_UUID7)

9.8.1 System Reset Status Register (SIM_SRS)

This register includes read-only status flags to indicate the source of the most recent
reset. When a debug host forces reset by writing 1 to the SIM_SBDFR[BDFR] bit, none
of the status bits in SRS will be set. The reset state of these bits depends on what caused
the MCU to reset.
For PIN, COP, and ILOP, any of these reset sources that are
active at the time of reset (not including POR or LVR) will
cause the corresponding bit(s) to be set; bits corresponding to
sources that are not active at the time of reset will be cleared.
The RESET values in the figure are values for power on reset;
for other resets, the values depend on the trigger causes.
Address: 1800h base + 0h offset = 1800h
Bit 7
Read POR
Write
Reset
1
Field
7 Power-On Reset
POR
Reset was caused by the power-on detection logic. When the internal supply voltage was ramping up at
the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the
internal supply was below the LVR threshold.
NOTE: This bit POR to 1, LVR to uncertain value and reset to 0 at any other conditions.
NXP Semiconductors
SIM memory map (continued)
Register name
NOTE
6 5
PIN WCOP ILOP
0 0
SIM_SRS field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 9 System Integration Module (SIM)
Width
Access
(in bits)
8
8
8
8
8
8
8
4 3
ILAD LOC
0 0
Description
Section/
Reset value
page
R Undefined 9.8.20/123
R Undefined 9.8.21/124
R Undefined 9.8.22/124
R Undefined 9.8.23/125
R Undefined 9.8.24/125
R Undefined 9.8.25/126
R Undefined 9.8.26/126
2 1
LVD FILA
0 1
0
0
105