Functional Description; Operational Modes; Fll Engaged Internal (Fei) - NXP Semiconductors MC9S08SU16 Reference Manual

12.4 Functional description

12.4.1 Operational modes

The seven states of the ICS are shown as a state diagram and are described below. The
arrows indicate the allowed movements among the states.
IREFS=0
CLKS=10
Debug Enabled
or LP =0
FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=10
Debug Disabled
and LP=1
Entered from any state
when MCU enters stop

12.4.1.1 FLL engaged internal (FEI)

FLL engaged internal (FEI) is the default mode of operation and is entered when all the
following conditions occur:
• 00b is written to ICS_C1[CLKS].
• 1b is written to ICS_C1[IREFS].
NXP Semiconductors
FLL Bypassed
External (FBE)
Figure 12-2. Clock switching modes
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
IREFS=1
CLKS=00
FLL Engaged
Internal (FEI)
FLL Engaged
External (FEE)
IREFS=0
CLKS=00
Stop
Chapter 12 Internal Clock Source (ICS)
IREFS=1
CLKS=01
Debug Enabled
or LP=0
FLL Bypassed
FLL Bypassed
Internal Low
Internal (FBI)
Power(FBILP)
IREFS=1
CLKS=01
Debug Disabled
and LP=1
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
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