Pdb0 Comparison High Register (Pdb_Cmph0) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions
Field
CMPL0 PDB0 low byte of the comparison value

23.6.4 PDB0 Comparison High Register (PDB_CMPH0)

The Comparison registers contain the high and low bytes of the comparison value for the
counter. After the counter reaches the comparison value, the timer comparison flag
(TCF0) becomes set at the next clock.
Writing to the CMPx0 registers would take effect immediately.
Address: 60h base + 3h offset = 63h
Bit 7
Read
Write
Reset 1
Field
CMPH0 PDB0 high byte of the comparison value
23.6.5 PDB0 Counter High/Low (PDB_CNT0)
The Counter registers may read the high or low bytes of the counter value which
controlled by [CNTSEL]. When BDM is active, the counter is frozen.
Reading either byte would not latch the contents of both bytes
into a buffer.
This register is also used to enable PDB0 by writing 1 to bit 0,
the writing operation doesn't take effect the counter's value.
Address: 60h base + 4h offset = 64h
Bit 7
Read
Write
Reset
0
428
PDB_CMPL0 field descriptions
NOTE
6 5
1 1
PDB_CMPH0 field descriptions
NOTE
6 5
CNT0_7_1
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
CMPH0
1 1
Description
4 3
0 0
2 1
1 1
2 1
CNT0_0_
PDBEN0
0 0
NXP Semiconductors
0
1
0
0