Port Filter Register 1 (Port_Ioflt1) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
Field
5–4 Filter selection for input from PTC
FLTC
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
3–2 Filter selection for input from PTB
FLTB
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
FLTA Filter selection for input from PTA
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3

8.5.13 Port Filter Register 1 (PORT_IOFLT1)

This register sets the filters for input.
Address: 0h base + 18EEh offset = 18EEh
Bit 7
Read
FLTKBI
Write
Reset 0
Field
7–6 Filter selection for input from KBI
FLTKBI
00 No filter
01 Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically.
10 Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically.
11 FLTDIV3
5–4 Filter selection for input from RESET
FLTRST
00 No filter.
01 Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically.
10 Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically.
11 FLTDIV3
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
94
PORT_IOFLT0 field descriptions (continued)
6 5
FLTRST
0 0
PORT_IOFLT1 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
0 0
Description
2 1
0
0 0
NXP Semiconductors
0
0