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Memory map and register definition
User software must disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
Address: 1800h base + Dh offset = 180Dh
Bit
7
Read
CMP0
Write
Reset
0
Field
7
CMP0 Clock Gate Control
CMP0
This bit controls the clock gate to the CMP0 module.
0
Bus clock to the CMP0 module is disabled.
1
Bus clock to the CMP0 module is enabled.
6
GDU_CMP Clock Gate Control
GDU_CMP
This bit controls the clock gate to the GDU_CMP module.
0
Bus clock to the GDU_CMP module is disabled.
1
Bus clock to the GDU_CMP module is enabled.
5
ADC1 Clock Gate Control
ADC1
This bit controls the clock gate to the ADC1 module.
0
Bus clock to the ADC1 module is disabled.
1
Bus clock to the ADC1 module is enabled.
4
ADC0 Clock Gate Control
ADC0
This bit controls the clock gate to the ADC0 module.
0
Bus clock to the ADC0 module is disabled.
1
Bus clock to the ADC0 module is enabled.
3
IRQ Clock Gate Control
IRQ
This bit controls the clock gate to the IRQ module.
0
Bus clock to the IRQ module is disabled.
1
Bus clock to the IRQ module is enabled.
2
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
1
PDB Clock Gate Control
PDB
This bit controls the clock gate to the PDB module.
118
6
5
GDU_CMP
ADC1
0
0
SIM_SCGC2 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NOTE
4
3
ADC0
IRQ
0
0
Description
2
1
0
PDB
KBI
0
0
NXP Semiconductors
0
0
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