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Field
1. Reset default
2
Internal Reference Select
IREFS
Selects the reference clock source for the FLL.
0
External reference clock is selected.
1
Internal reference clock is selected.
1
Internal Reference Clock Enable
IRCLKEN
Enables the internal reference clock for use as ICSIRCLK.
0
ICSIRCLK is inactive.
1
ICSIRCLK is active.
0
This field is reserved.
Reserved
1. Reset default
12.3.2 ICS Control Register 2 (ICS_C2)
Address: 1848h base + 1h offset = 1849h
Bit
7
Read
Write
Reset
0
Field
7–5
Bus Frequency Divider
BDIV
Selects the amount to divide down the clock source selected by ICS_C1[CLKS]. This controls the bus
frequency.
000
Encoding 0—Divides the selected clock by 1.
001
Encoding 1—Divides the selected clock by 2 (reset default).
010
Encoding 2—Divides the selected clock by 4.
011
Encoding 3—Divides the selected clock by 8.
100
Encoding 4—Divides the selected clock by 16.
101
Encoding 5—Divides the selected clock by 32.
NXP Semiconductors
ICS_C1 field descriptions (continued)
RDIV
SIM_SOPT1[RANGE]= 0
100
101
110
111
6
5
BDIV
0
1
ICS_C2 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 12 Internal Clock Source (ICS)
Description
16
32
64
128
4
3
LP
0
0
Description
SIM_SOPT1[RANGE]= 1
512
1024
Reserved
Reserved
2
1
0
0
0
0
0
193
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