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Functional description
9
8
7
6
5
4
3
Up Counter
2
1
Modulus = 9
PWM VAL0 = 3; CINV0 =0
PWM VAL1 = 6; CINV1 =0
PWM0
Figure 26-16. Variable edge placement waveform - phase shift PWM output
26.3.7 PWM output polarity
Positive polarity means when the PWM is active its output is high. Conversely, negative
polarity means when the PWM is active its output is low.
Output polarity of the PWMs is determined by two options:
• TOPNEGnn controls the polarity of PWM0, PWM2 and PWM4 outputs, which
typically drive the top transistors of the pair. When TOPNEGnn is set these outputs
are active-low.
• BOTNEGnn controls the polarity of PWM1, PWM3 and PWM5 outputs, which
typically drive the bottom transistors of the pair. When BOTNEGnn is set these
outputs are active-low.
Both TOPNEGnn and BOTNEGnn bits are in the configure (CNFG) register. Software
Output Control
Setting output control enable (OUTCTRLn) bit, the PWM outputs are driven by software
rather than by the PWM generator.
In an independent mode, with OUTCTRLn=1, the output bit OUTn, controls the PWMn
channel. Setting and clearing the OUTn bit activates and deactivates the corresponding
PWM channel.
The OUTCTRLn and OUTn bits are in the PWM output control (OUT) register.
During software output control, TOPNEGnn and BOTNEGnn still control output
polarity.
494
PWM VAL0 = 3; CINV0 =0
PWM VAL1 = 7; CINV1 =0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
PWM VAL0 = 3; CINV0 =0
PWM VAL0 = 7; CINV1 =1
NXP Semiconductors
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