System Port A Pin Multiplexing Control Register: Low (Sim_Muxptal) - NXP Semiconductors MC9S08SU16 Reference Manual

9.8.7 System Port A Pin Multiplexing Control Register: Low
(SIM_MUXPTAL)
Many of the I/O pins are shared with on-chip peripheral functions. This register selects
the multiplexing pin functions from ALT0 to ALT3. Default is ALT0 function, When the
Pin Muxing mode is configured for analog pins, all the digital functions on that pin are
disabled, including the pullup/output/input.
The shared analog pin functions can work together if they're enabled separately because
they're directly connected to internal analog modules separately. They still work even
when pin Muxing mode is configured for digital pins.
KBI share with PTA on ALT3 and can be enable/disable by
KBI_PE register.
"RX and CLK_IN" function at different location must not be
selected at the same time to prevent signal override or
modulation.
Address: 1800h base + 6h offset = 1806h
Bit 7
Read
MUXPTA3
Write
Reset 0
Field
7–6 Pin Mux Control
MUXPTA3
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
5–4 Pin Mux Control
MUXPTA2
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
3–2 Pin Mux Control
MUXPTA1
NXP Semiconductors
NOTE
6 5
MUXPTA2
0 0
SIM_MUXPTAL field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 9 System Integration Module (SIM)
4 3
MUXPTA1
0 0
Description
2 1
MUXPTA0
0 0
0
0
111