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Field
0
No channel event has occurred.
1
A channel event has occurred.
6
Channel Interrupt Enable
CHIE
Enables channel interrupts.
0
Disable channel interrupts. Use software polling.
1
Enable channel interrupts.
5
Channel Mode Select
MSB
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
the table in the register description.
4
Channel Mode Select
MSA
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
the table in the register description.
3
Edge or Level Select
ELSB
The functionality of ELSB and ELSA depends on the channel mode. See the table in the register
description.
2
Edge or Level Select
ELSA
The functionality of ELSB and ELSA depends on the channel mode. See the table in the register
description.
1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
19.4.9 Channel Value High (FTMx_CnVH)
These registers contain the captured FTM counter value of the input capture function or
the match value for the output modes.
In input capture mode, reading a single byte in CnV latches the contents into a buffer
where they remain latched until the other byte is read. This latching mechanism also
resets, or becomes unlatched, when the CnSC register is written whether BDM mode is
active or not. Any write to the channel registers is ignored during this mode.
When BDM is active, the read coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active, even if one or both
bytes of the channel value register are read while BDM is active. This ensures that if you
were in the middle of reading a 16-bit register when BDM became active, it reads the
appropriate value from the other half of the 16-bit value after returning to normal
execution. Any read of the CnV registers in BDM mode bypasses the buffer latches and
returns the value of these registers and not the value of their read buffer.
NXP Semiconductors
FTMx_CnSC field descriptions (continued)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 19 FlexTimer Module (FTM)
Description
327
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