Pulse Width Timer Control Register (Pwtx_Cr) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions
Field
5 PWT Pulse Width Data Ready Interrupt Enable
PRDYIE
Enables/disables the PWT to generate an interrupt when PWTRDY is set as long as PWTIE is set.
0 Disable PWT to generate interrupt when PWTRDY is set.
1 Enable PWT to generate interrupt when PWTRDY is set.
4 PWT Counter Overflow Interrupt Enable
POVIE
Enables/disables the PWT to generate an interrupt when PWTOV is set due to PWT counter overflow.
0 Disable PWT to generate interrupt when PWTOV is set.
1 Enable PWT to generate interrupt when PWTOV is set.
3 PWT Soft Reset
PWTSR
Performs a soft reset to the PWT. This field always reads as 0.
0 No action taken.
1 Writing 1 to this field will perform soft reset to PWT.
2 First counter load enable after enable
FCTLE
This bit determines if the counter value should be loaded to the corresponding PWTx_PPW{H,L},
PWTx_NPW{H,L} after first enable.
0 Do not load the first counter values to corresponding registers
1 Load the first coutner value to corresponding registers depended by the PWTIN level
1 PWT Pulse Width Valid
PWTRDY
Indicates that the PWT Pulse Width register(s) has been updated and is ready to be read. This field is
cleared by reading PWTRDY and then writing 0 to PWTRDY bit when PWTRDY is set.Writing 1 to this
field has no effect.
0 PWT pulse width register(s) is not up-to-date.
1 PWT pulse width register(s) has been updated.
0 PWT Counter Overflow
PWTOV
Indicates that the PWT counter has run from 0x0000_0xFFFF to 0x0000_0x0000. This field is cleared by
writing 0 to PWTOV when PWTOV is set. Writing 1 to this field has no effect. If another overflow occurs
when this field is being cleared, the clearing fails.
0 PWT counter no overflow.
1 PWT counter runs from 0xFFFF to 0x0000.

20.4.2 Pulse Width Timer Control Register (PWTx_CR)

Address: Base address + 1h offset
Bit 7
Read
PCLKS
Write
Reset 0
348
PWTx_CS field descriptions (continued)
6 5
TGL
PINSEL
w1c
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
LVL
0 0
2 1
PRE
0 0
NXP Semiconductors
0
0