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Related Manuals for NXP Semiconductors MC9S12VRP64
Summary of Contents for NXP Semiconductors MC9S12VRP64
- Page 1 MC9S12VRP-Series Reference Manual and Datasheet S12 MagniV Microcontrollers MC9S12VRP64 Rev. 1.3 19 Sep 2017 nxp.com...
- Page 2 Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://nxp.com A full list of family members and options is included in the device overview section. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the CPU.
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Page 3: Table Of Contents
1.11.3 Effects of Reset ............43 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 4 External Signal Description ............95 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 5 Interrupts ..............164 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 6 6.4.2 Comparator Modes ........... . 215 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 7 8.1.2 Modes of Operation ........... . 247 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 8 10.4.1 Infrared Interface Submodule ..........318 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 9 12.3 Memory Map and Register Definition ..........362 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 10 14.1.1 Features ............. 383 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 11 16.2.4 LPTxD — LIN Transmit Pin ..........406 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 12 18.4.4 Flash Command Operations ..........464 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 13 C.3.1 ADC Accuracy Definitions..........512 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 14 L.4 0x000E-0x000F Reserved ............536 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 15 L.25 0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4 ......551 L.26 0x02F0-0x02FF Clock and Power Management Unit (CPMU) Map 2 of 2....554 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 16 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 17: Introduction
I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. The S12VRP-Series is targeted at relay based motor control automotive applications requiring single node LIN communications. Typical examples of these applications include: MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 18: Features
Frequency modulated PLL Internal 1 MHz RC oscillator Autonomous window watchdog Low side driver (relay driver) Low side driver (general) High side driver Current sense amplifier High voltage Inputs Direct Battery sense pin, Vsense MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 19: Chip-Level Features
Autonomous periodic interrupt (API) (combined with watchdog) • Two protected low-side driver outputs to drive inductive loads (VSUP domain) • One further 20mA low-side driver output (VSUP domain) • Two protected high-side driver outputs (VSUP domain) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 20: Module Features
— Single bit error correction and double fault detection within a word during read operations — Erase sector size 256 bytes — Automated program and erase algorithm with verify and generation of ECC parity bits — Protection scheme to prevent accidental program or erase MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 21: On-Chip Sram
— Reference clock sources: – Internal 1 MHz RC oscillator (IRC) – External crystal oscillator 1.5.7 Clock and Power Management Unit (CPMU) • Real time interrupt (RTI) • Clock monitor (CM) • System reset generation MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 22: System Integrity Support
Fulfills the OEM “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications” v1.3 • Internal connection to one SCI 1.5.12 Serial Communication Interface Module (SCI) • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 23: Analog-To-Digital Converter Module (Adc)
— Low-voltage detect with low-voltage interrupt on VSUP — Capable of supplying both the MCU internally and providing additional external current (approximately 20mA) to supply other components within the electronic control unit. — Over-temperature interrupt MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 24: Low-Side Driver (Lsdrv)
Open load detection • Programmable slew rate control 1.5.20 Background Debug (BDM) • Background debug module (BDM) with single-wire interface — Non-intrusive memory access commands — Supports in-circuit programming of on-chip nonvolatile memory MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 25: Debugger (Dbg)
LIN Physical Layer LGND LGND Block Diagram shows the maximum configuration! Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. Figure 1-1. S12VRP-Series Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 26: Family Memory Map
LSDRV (low-side driver) 0x0158–0x015F LS2DRV 0x0160–0x0167 LINPHY (LIN physical layer) 0x0168–0x016F Reserved 0x0170–0x0177 BATS (supply voltage sense) 0x0178–0x017F ISENSE (current sense amplifier) 0x0180–0x01AF TIM1 (timer module) 0x01B0–0x023F Reserved 0x0240–0x027F PIM (port integration module) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 27 6 KB 0x2800-0x3FFF S12VRP64 Data Flash 4 KB 0x0400-0x13FF Program Flash 64KB Page C, D, E and F NOTE Flash space on page 0xC in Figure 1-2 is not available on S12VRP48. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 28 Page 0xC Page 0xC 0x3_4000 0xFFFF P-Flash Space Page 0xD Page 0xD 0x3_8000 P-Flash Space Page 0xE Page 0xE 0x3_C000 P-Flash Space Page 0xF Page 0xF 0x3_FFFF Figure 1-2. S12VRP-Series Global Memory Map. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 29: Part Id Assignments
To avoid current drawn from floating inputs, all non-bonded pins should be configured as output or configured as input with a pull up or pull down device enabled 1.8.2 Detailed Signal Descriptions This section describes the signal properties. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 30 PT[3:0] — Port T I/O Signals PT[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 31 LINPHY Signals 1.8.2.17.1 VLINSUP — Positive Power Supply This is the power supply to the LINPHY. VLINSUP is connected internally to VSUP. 1.8.2.17.2 LPTXD Signal This signal is the LINPHY transmit input. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 32: Power Supply Pins
S12VRP-Series power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 33 5V power supply output for I/O drivers generated by on chip voltage regulator VSSX1 Ground pin for I/O drivers VDDX2 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 34: Device Pinouts
Ground pin for low-side driver VSUP 12V/18V External power supply for voltage regulator and high-side driver supply 1.8.4 Device Pinouts S12VRP-Series is available in a 48-pin package. Signals in parentheses in denote alternative module routing options. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 35: Mc9S12Vrp Pinout 48-Pin Lqfp
VSENSE VDDX1 RXD1 / (RXD0) / PS0 VSSX2 TXD1 / (LPDR1) / (TXD0) / PS1 (RXD1) / (PWM4) / (ETRIG0) / PS2 VSUP MODC / BKGD Figure 1-3. MC9S12VRP 48-pin LQFP pinout MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 36 PWM5 PERP/ PPSP — — — — — — — EXTAL — — — PUCR/ Down PUPEE XTAL — — — PUCR/ Down PUPEE VDDX2 — — — — — — — MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 37 PER1AD/ PPS1AD PAD3 KWAD3 — — PER1AD/ PPS1AD PAD2 KWAD2 AMPP0 — PER1AD/ PPS1AD PAD1 KWAD1 AMPM0 — PER1AD/ PPS1AD PAD0 KWAD0 AMP0 — PER1AD/ PPS1AD IOC0_0 PWM6 RXD0 — PERT/ PPST MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 38 LPRXD API_EX — PERT/ TCLK PPST IOC1_1 LPTXD — — PERT/ PPST ETRIG1 PWM5 TXD1 ECLK PERS/ PPSS PGPIO is EVDD type, capable of driving up to 20KHz into logic level FET. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 39: Modes Of Operation
— Run mode is the main full performance operating mode with the entire device clocked. The user can configure the device operating speed through selection of the clock source and the phase locked loop (PLL) frequency. To save power, unused peripherals must not be enabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 40: Security
Table 1-10. Reset Sources and Vector Locations Vector Address Reset Source Local Enable Mask Power-On Reset (POR) None None $FFFE Low Voltage Reset (LVR) None None $FFFE External pin RESET None None $FFFE MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 41: Interrupt Vectors
TIM1 timer overflow I bit TIM1TSCR2(TOF) Vector base + $DA Reserved Vector base + $D8 Vector base+ $D6 SCI0 I bit SCI0CR2 RXEDGIF (TIE, TCIE, RIE, ILIE) only SCI0ACR1 (RXEDGIE, BERRIE, BKDIE) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 42 Port P2 and P0 over-current interrupt I bit PIEP (OCIEP2, OCIEP0) Vector base + $8A Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) Vector base + $88 Autonomous periodical interrupt (API) I bit CPMUAPICTRL (APIE) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 43: Effects Of Reset
ETRIG0 is connected to PP4 / PWM4 and ETRIG1 is connected to PP5 / PWM5. ETRIG2 and ETRIG3 are not used. ETRIG0 can be routed to PS2 and ETRIG1 can be routed to PS3. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 44: Adc Special Conversion Channels
Flash configuration field byte at global address 0x3_FF0E during the reset sequence. See Table 1-13 Table 1-14 for coding. Table 1-13. Initial COP Rate Configuration NV[2:0] in CR[2:0] in FOPT Register COPCTL Register MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 45: Cpmu High Temperature Trimming
ACLKTR[5:0] HTTR[3:0] 0x40B8 - 0x40B9 TCTRIM[4:0] IRCTRIM[9:0] 0x40BA -0x40BB Section 4.3.2.16 Autonomous Clock Trimming Register (CPMUACLKTR) Section 4.3.2.19 High Temperature Trimming Register (CPMUHTTR) Section 4.3.2.20 S12CPMU_UHV_V8 IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 46 Device Overview S12VRP-Series MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 47: Chapter 2
• Internal test feature update V00.10 11 Aug 2016 2.4.7.2/86 • Specified RC OSC not dependent on interrupt enables V00.11 02 Aug 2017 Table 2-3 • Corrected typos and formating Table 2-10 Table 2-11 Table 2-13 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 48: Introduction
PAD5 PTAD4 PAD4 PTAD3 PAD3 PTAD2 AMPP0 PAD2 PTAD1 AMPM0 PAD1 PTAD0 AMP0 PAD0 • Port E External GPIO Pins Oscillator PTE1 XTAL PTE0 EXTAL • Port L HVI/KWU Pins PTIL5 AN11 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 49 PWM2 PTP1 PWM1 XIRQ PTP0 PWM0 • Port S GPIO ETRIG SCI0 LINPHY SCI1 CLOCK Pins PTS3 ETRIG1 PWM5 TXD1 ECLK PTS2 ETRIG0 PWM4 RXD1 PTS1 TXD0 LPDR1 TXD1 PTS0 RXD0 RXD1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 50: Features
— SCI0 and SCI1 to alternative pins — Various SCI0-LINPHY routing options for standalone use and conformance testing — Internal SCI0/LINPHY link to TIM1 input capture channel (IC1_1) for baud rate detection MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 51: External Signal Description
Func. Pin Function Routing Port Description after & Priority Register Bit Reset — BKGD MODC MODC input during RESET — BKGD BKGD I/O BDM communication pin — Function active when RESET asserted MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 52 Pin Function Routing Port Description after & Priority Register Bit Reset XTAL — CPMU OSC signal — GPIO PTE[1] I/O GPIO — EXTAL — CPMU OSC signal — PTE[0] I/O GPIO — MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 53 HVI with pin-interrupt with — KWL[2]/ key-wakeup and ADC analog input PTL[1]/ HVI with pin-interrupt with — KWL[1]/ key-wakeup and ADC analog input PTL[0]/ HVI with pin-interrupt with — KWL[0]/ key-wakeup and ADC analog input MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 54 Switchable external power supply output EVDD (10mA) PWM0 PWM channel 0 with over current interrupt — PTP[0]/ I/O GPIO with interrupt and wakeup — KWP[0]/ Switchable external power supply output EVDD (20mA) with over-current interrupt MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 55 LS1RR1-0 IOC0_1 I/O TIM0 channel 1 LS1RR1-0 (OC0_1) PTT[1] I/O GPIO — (RXD0) SCI0 receive MODRR23-20 PWM6 PWM channel 6 LS0RR1-0 IOC0_0 I/O TIM0 channel 0 LS0RR1-0 (OC0_0) PTT[0] I/O GPIO — MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 56: Memory Map And Register Definition
This section provides a detailed description of all port integration module registers. Subsection 2.3.1 shows all registers and bits at their related addresses within the global device register map. A detailed description of every register bit is given in subsections 2.3.2 to 2.3.4. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 57: Register Map
Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0020– Non-PIM Non-PIM Address Range 0x023F Address Range 0x0240 PTT3 PTT2 PTT1 PTT0 PTIT3 PTIT2 PTIT1 PTIT0 0x0241 PTIT 0x0242 DDRT DDRT3 DDRT2 DDRT1 DDRT0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 58 0x024E WOMS WOMS3 WOMS2 WOMS1 WOMS0 0x024F MODRR2 MODRR27 MODRR24 MODRR23 MODRR22 MODRR21 MODRR20 0x0250– Reserved 0x0257 0x0258 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 0x0259 PTIP MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 59 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0 0x0269 PTIL 0x026A DIENL DIENL5 DIENL4 DIENL3 DIENL2 DIENL1 DIENL0 0x026B PTTEL PTTEL5 PTTEL4 PTTEL3 PTTEL2 PTTEL1 PTTEL0 0x026C PIRL PIRL5 PIRL4 PIRL3 PIRL2 PIRL1 PIRL0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 60 Reserved 0x0278 0x0279 PER1AD PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 0x027A Reserved 0x027B PPS1AD PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 0x027C Reserved 0x027D PIE1AD PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 0x027E Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 61: Device Specific Pim Registers
01 TIM1 output compare channel 1 routed to LS2 if enabled. If OC1_1 is routed to HS1 then this bit has no effect. 00 LS2 controlled by register bit LS2DR[LSDR]. See Chapter 14, “Low-Side Driver - LS2DRV (S12LS2DRV_V1)” MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 62 If PWM channel 4 is routed to HS1, then this bit has no effect on PWM mapping but ETRIG0 is still mapped by this bit. 1 PWM channel 4 on PS2; ETRIG0 on PS2 0 PWM channel 4 on PP4; ETRIG0 on PP4 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 63 0 TIM1 input capture channel 1 is connected to PT3 MODule Routing Register 2 — SCI1 routing MODRR22 1 TXD1 on PS3; RXD1 on PS2 0 TXD1 on PS1; RXD1 on PS0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 64 Figure 2-4. SCI0 to LINPHY Routing Options Illustration Table 2-14. Preferred Interface Configurations MODRR2[2:0] Description Default setting: SCI0 connects to LINPHY, interface internal only Direct control setting: LPDR[LPDR1] register bit controls LPTXD, interface internal only MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 65 This bit configures whether a pulldown device is activated on all associated port input pins. If a pin is used as output or used with the CPMU OSC function this bit has no effect. Out of reset the pulldown devices are enabled. 1 Pullup devices enabled 0 Pullup devices disabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 66 Write: Only in special mode This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the module’s functionality. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 67 IRQE=1 and are cleared only upon a reset or the servicing of the IRQ interrupt. 0 IRQ configured for low level recognition IRQ enable — IRQEN 1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interrupt logic MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 68: Pim Generic Registers
E.g. a pull-up device does not become active while the port is used as a push-pull output. • General-purpose data output availability depends on prioritization; input data registers always reflect the pin status independent of the use. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 69 Port Input Register Address 0x0273 PTI1AD Access: User read only 0x0259 PTIP 0x0249 PTIS 0x0241 PTIT PTIx7 PTIx6 PTIx5 PTIx4 PTIx3 PTIx2 PTIx1 PTIx0 Reset Figure 2-12. Port Input Register Read: Anytime Write:Never MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 70 Note: Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct value is read on port data and port input registers, when changing the data direction register. 1 Associated pin is configured as output 0 Associated pin is configured as input MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 71 Polarity Select Register Address 0x027B PPS1AD Access: User read/write 0x025D PPSP 0x024D PPSS 0x0245 PPST PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0 Reset Figure 2-15. Polarity Select Register Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 72 Port Interrupt Flag Register Address 0x027F PIF1AD Access: User read/write 0x026F PIFL PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0 Reset Figure 2-17. Port Interrupt Flag Register Read: Anytime Write: Anytime, write 1 to clear MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 73 This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on the pin. 1 Reduced drive selected 0 Full drive strength enabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 74: Pim Generic Register Exceptions
Figure 2-20. PIM Reserved Register Read: Always reads 0x00 Write: Unimplemented 2.3.4 PIM Generic Register Exceptions This section lists registers with deviations from the generic description in one or more register bits. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 75 Port P Interrupt Enable Register (PIEP) Address 0x025E PIEP Access: User read/write OCIEP2 OCIEP0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 Reset Figure 2-22. Port P Interrupt Enable Register Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 76 This flag asserts if an over-current condition is detected on PP2 (Section 2.4.7.3, “Over-Current Interrupt and Protection”). Writing a logic “1” to the corresponding bit field clears the flag. 1 PP2 over-current event occurred 0 No PP2 over-current event occurred MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 77 Note: When enabling the resistor paths to ground by setting PTAENL=1, a delay of t + two bus cycles must UNC_HVI be accounted for. 1 ADC connection enabled 0 ADC connection disabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 78 This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1). 1 Impedance converter bypassed 0 Impedance converter used MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 79 Section 2.3.4.11, “Port L Input Divider Ratio Selection Register (PIRL)”. A one is read in any other case Refer to PTTEL bit description in Section 2.3.4.10, “Port L Test Enable Register (PTTEL) for an override condition. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 80 1 Associated pin digital input is enabled if not used as analog input in run mode 0 Associated pin digital input is disabled Refer to PTTEL bit description in Section 2.3.4.10, “Port L Test Enable Register (PTTEL) for an override condition. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 81 When enabling the resistor paths to ground by setting PTAENL=1 or, a settling time of t + two bus cycles must be considered to let internal UNC_HVI nodes be loaded with correct values. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 82: Functional Description
1 Rising edge selected 0 Falling edge selected Functional Description 2.4.1 General Each pin except BKGD and port L pins can act as general-purpose I/O. In addition each pin can act as an MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 83: Registers
I/O or with a shared peripheral function. If the pin is configured as input (DDRx=0, Section 2.3.3.3, “Data Direction Register”), the pin state can also be read through the data register (PTx, Section 2.3.3.1, “Port Data Register”). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 84 If applicable the appropriate routing configuration must be set for the signals to take effect on the pins. DDR maintains control To use the digital input function the related bit in Digital Input Enable Register (DIENAD) must be set to logic level “1”. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 85: Pull Devices
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are defined at MCU level. Table 2-41. PIM Interrupt Sources Module Interrupt Sources Local Enable XIRQ None IRQCR[IRQEN] MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 86 Please refer to the “Pin Interrupt Characteristics” in the device electrical specification for pulse length limits. To reduce current consumption the RC oscillator is active only for a short phase following a detected edge on any pin whose interrupt flag is not set (PIF[x]=0). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 87: High-Voltage Input
Open input detection. Figure 2-35 shows a block diagram of the HVI. NOTE The term stop mode (STOP) is limited to voltage regulator operating in reduced performance mode (RPM). Refer to device overview information. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 88 PTIL. An interrupt flag (PIFL) is set on input TH_HVI transitions if enabled (PIEL=1) and configured for the related edge polarity (PPSL). Wakeup from stop mode is supported. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 89: Initialization And Application Information
The baud rate for SCI0 can be determined by using a timer channel to measure the data rate on the related RXD signal. 1. Establish the link: set MODRR2[MODRR27]=1 to route TIM1 input capture channel 1 to internal RXD0 signal of SCI0. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 90: Over-Current Protection On Pp2 And Pp0
2. Select internal pull-up device on HVI (PTPSL=1) 3. Enable function to force input buffer active on HVI in analog mode (PTTEL=1) 4. Verify PTIL=0 for a connected external pulldown device; read PTIL=1 for an open input MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 91 4. Verify PTIL=1 for a connected external pull-up device; read PTIL=0 for an open input HV Supply 140K max. 17/22 * V (PIRL=0) max. 19/22 * V (PIRL=1) Digital in 510K / 950K PIRL=0 / PIRL=1 Figure 2-37. Digital Input Read with Pulldown Enabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 92 Port Integration Module (S12VRPPIMV1) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 93: Introduction
(memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 94: Features
S12VRP devices can be secured to prohibit external access to the on-chip flash. The S12GMMC module determines the access permissions to the on-chip memories in secured and unsecured state. 3.1.5 Block Diagram Figure 3-1 shows a block diagram of the S12GMMC. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 95: External Signal Description
Module Memory Map A summary of the registers associated with the S12GMMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 96: Register Descriptions
This section consists of the S12GMMC control register descriptions in address order. 3.3.2.1 Mode Register (MODE) Address: 0x000B MODC Reset MODC 1. External signal (see Table 3-3). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 97 Write: anytime in special SS, write-once in NS. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 98 This bit maps internal NVM resources into the global address space. 0 Program flash is mapped to the global address range from 0x04000 to 0x07FFF. 1 NVM resources are mapped to the global address range from 0x04000 to 0x07FFF. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 99 The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0xC. Parts of this page are covered by Registers, D-Flash and RAM space. See SoC Guide for details. The fixed 16KB page from 0x4000–0x7FFF is the page number 0xD. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 100: Functional Description
(PPAGE[3:0]) to page 16x16 KB blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 101 The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for further details. (see Figure 3-10). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 102 Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] BDM Local Address [13:0] BDM FIRMWARE COMMAND Global Address [17:0] Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] CPU Local Address [13:0] Figure 3-10. Figure 3-11. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 103 P-Flash Space Page 0xD Page 0xD 0x3_8000 P-Flash Space P-Flash Space Page 0xE Page 0xE 0x3_C000 P-Flash Space P-Flash Space Page 0xF Page 0xF 0x3_FFFF Figure 3-12. Local to Global Address Mapping MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 104: Unimplemented And Reserved Address Ranges
Unimplemented 0x027FF 0x02800- 0x03FFF 0x04000- Internal NVM Resources 0x07FFF (for details refer to section (NVMRES FTMRG) 0x04000- 0x07FFF (NVMRES Unimplemented 0x08000- 0x30000 0x30000- Reserved 0x33FFF 0x34000- 0x37FFF 0x38000- P-Flash 0x3BFFF 0x3C000- 0x3FFFF MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 105: Prioritization Of Memory Accesses
BDM accesses unless the BDM module has been stalled for more then 128 bus cycles. In this case the pending BDM access will be processed immediately. 3.4.5 Interrupts The S12GMMC does not generate any interrupts. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 106 S12G Memory Map Controller (S12GMMCV1) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 107: Introduction
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. • The Internal Reference Clock (IRC1M) provides a 1MHz internal clock. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 108: Features
The Internal Reference Clock (IRC1M) has the following features: • Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after reset, which can be overwritten by application if required) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 109 — Low-voltage reset (LVR) — Illegal address access — COP time-out — Loss of PLL clock (PLL clock monitor fail) — Loss of oscillation (Oscillator clock monitor fail) — External pin RESET MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 110: Modes Of Operation
PLL configuration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL configuration is valid for the selected oscillator frequency. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 111 CSAD. When bit CSAD is set the ACLK clock source for the COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 112 Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description field of Table 4-13 Section 4.3.2.9, “S12CPMU_UHV_V8 COP Control Register (CPMUCOP) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 113: S12Cpmu_Uhv_V8 Block Diagram
Osc. RTI Interrupt RTIE COP time-out COPCLK IRCCLK to Reset Watchdog Generator IRCCLK Real Time OSCCLK RTICLK Interrupt (RTI) OSCCLK CPMUCOP COPOSCSEL0 RTIOSCSEL CPMURTI UPOSC=0 clears Figure 4-1. Block diagram of S12CPMU_UHV_V8 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 114 XOSCLCP. OSCCLK_LCP OSC monitor fail Clock Monitor Peak Gain Control Detector VDD = 1.8 V Quartz Crystals XTAL EXTAL Ceramic Resonators Figure 4-2. XOSCLCP Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 115: Signal Description
4.2.5 VDDX, VSSX— Pad Supply Pins This supply domain is monitored by the Low Voltage Reset circuit. A local decoupling capacitor between VDDX and VSSX according to the electrical specification is required. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 116: Vss— Ground Pin
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel input of the ADC Converter. See device level specification for connectivity of ADC special channels. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 117: Memory Map And Registers
Bit 0 HTDS CPMU 0x02F0 VSEL HTIE HTIF HTCTL LVDS CPMU 0x02F1 LVIE LVIF LVCTL CPMU 0x02F2 APICLK APIES APIEA APIFE APIE APIF APICTL = Unimplemented or Reserved Figure 4-3. CPMU Register Summary MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 118 0x02F8 TCTRIM[4:0] IRCTRIM[9:8] IRCTRIMH CPMU 0x02F9 IRCTRIM[7:0] IRCTRIML 0x02FA CPMUOSC OSCE 0x02FB CPMUPROT PROT RESERVED 0x02FC CPMUTEST2 0x02FD RESERVED 0x02FE CPMUOSC2 OMRE OSCMOD = Unimplemented or Reserved Figure 4-3. CPMU Register Summary MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 119: Register Descriptions
4-2. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 4-2. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= f <= 48MHz 48MHz < f <= 50MHz Reserved Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 120 Table 4-3. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges REFFRQ[1:0] (OSCE=1) 1MHz <= f <= 2MHz 2MHz < f <= 6MHz 6MHz < f <= 12MHz >12MHz MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 121 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset. = Unimplemented or Reserved Figure 4-7. S12CPMU_UHV_V8 Flags Register (CPMUFLG) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 122 Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop UPOSC Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualified by the PLL. 1 The oscillator is qualified by the PLL. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 123 PLL Clock Monitor Reset Flag — PMRF is set to 1 when a loss of PLL clock occurs. This flag can only be PMRF cleared by writing a 1. Writing a 0 has no effect. 0 Loss of PLL clock reset has not occurred. 1 Loss of PLL clock reset has occurred. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 124 (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the external oscillator clock is used as system clock, the system might stall in case of loss of oscillation. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 125 1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1 Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 126 UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK. 1 COP clock source is OSCCLK Table 4-7. COPOSCSEL1, COPOSCSEL0 clock source select description COPOSCSEL1 COPOSCSEL0 COP clock source IRCCLK OSCCLK ACLK MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 127 The modulation frequency is f divided by 16. See Table 4-9 for coding. Table 4-9. FM Amplitude selection FM Amplitude / Variation FM off 1% 2% 4% MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 128 Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to RTR[3:0] provide additional granularity.Table 4-11 Table 4-12 show all possible divide values selectable by the CPMURTI register. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 129 15x2 1110 (15) 16x2 16x2 16x2 16x2 16x2 16x2 16x2 1111 (16) Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 130 1100 (13) 14x10 28x10 70x10 140x10 280x10 700x10 1.4x10 2.8x10 1101 (14) 15x10 30x10 75x10 150x10 300x10 750x10 1.5x10 3x10 1110 (15) 16x10 32x10 80x10 160x10 320x10 800x10 1.6x10 3.2x10 1111 (16) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 131 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 132 4) Operation in Special Mode Table 4-14. COP Watchdog Rates if COPOSCSEL1=0. (default out of reset) COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) COP disabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 133 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8) Table 4-15. COP Watchdog Rates if COPOSCSEL1=1. COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) COP disabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 134 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V8’s functionality. 0x003E Reset = Unimplemented or Reserved Figure 4-14. Reserved Register (CPMUTEST1) Read: Anytime Write: Only in Special Mode MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 135 0x02F0 HTDS VSEL HTIE HTIF Reset = Unimplemented or Reserved Figure 4-16. High Temperature Control Register (CPMUHTCTL) Read: Anytime Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 136 1 HTDS bit has changed. NOTE The voltage at the temperature sensor can be computed as follows: (temp) = V - (150 - temp) * dV HT(150) Figure 4-17. Voltage Access Select TEMPSENSE VSEL Channel MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 137 Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by LVIF writing a 1.Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 138 This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 139 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8) Figure 4-20. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 140 ACLK period time. Table 4-20. Trimming Effect of ACLKTR[5:0] ACLKTR[5:0] Decimal ACLK frequency 100000 lowest 100001 increasing ..111111 000000 000001 increasing ..011110 011111 highest MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 141 For APICLK bit clear the first time-out period of the API will show a latency time between two to three f cycles due to synchronous clock ACLK gate release when the API feature gets enabled (APIFE bit set) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 142 12 * Bus Clock period ..FFFD 131068 * Bus Clock period FFFE 131070 * Bus Clock period FFFF 131072 * Bus Clock period When f is trimmed to 20kHz. ACLK MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 143 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V8’s functionality. 0x02F6 Reset = Unimplemented or Reserved Figure 4-24. Reserved Register (CPMUTEST3) Read: Anytime Write: Only in Special Mode MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 144 HTTR[3:0] Table 4-25. Trimming Effect of HTTR Temperature Interrupt threshold HTTR[3:0] sensor voltage V temperatures T and T HTIA HTID 0000 lowest highest 0001 increasing decreasing ..1110 1111 highest lowest MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 145 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 4-28 shows the relationship between the trim bits and the resulting IRC1M frequency. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 146 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8) IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 4-28. IRC1M Frequency Trimming Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 147 Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 148 NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 149 Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t before entering Pseudo Stop Mode. UPOSC MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 150 (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit. 0 Protection of clock configuration registers is disabled. 1 Protection of clock configuration registers is enabled. (see list of protected registers above). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 151 OSCMOD Reset Figure 4-33. S12CPMU_UHV_V8 Oscillator Register 2 (CPMUOSC2) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register),PLLSEL=1 (CPMUCLKS register) and OSCE=0 (OSCCLK Enable Bit in CPMUOSC register). Else write has no effect. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 152 1 Oscillator clock monitor reset is enabled 0 External oscillator configured for loop controlled mode (reduced amplitude on EXTAL and XTAL) OSCMOD 1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 153: Functional Description
If PLL is selected (PLLSEL=1) f bus ------------ - NOTE Although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 154 , and is cleared when Lock the VCO frequency is out of the tolerance, • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 155: Startup From Reset
Bus Clock = Core Clock/2 lock LOCK $18 (default target f =50MHz) SYNDIV $03 (default target f /4 = 12.5MHz) POSTDIV example change reset state startup vector fetch, program execution of POSTDIV cycles STARTUP MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 156: Stop Mode Using Pllclk As Source Of The Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 4-36. Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 157 Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 158: External Oscillator
OSCCLK UPOSC flag is set upon successful start of oscillation UPOSC UPOSC select OSCCLK as Core/Bus Clock by writing PLLSEL to zero PLLSEL based on OSCCLK based on PLL Clock Core Clock MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 159: System Clock Configurations
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 160: Resets
4-31. Refer to MCU specification for related vector addresses and priorities. Table 4-31. Reset Summary Reset Source Local Enable Power-On Reset (POR) None Low Voltage Reset (LVR) None External pin RESET None Illegal Address Reset None MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 161: Description Of Reset Operation
External pin RESET Oscillator Clock Monitor Reset COP Reset Illegal Address Reset PLL Clock Monitor Reset External pin RESET NOTE While System Reset is asserted the PLLCLK runs with the frequency VCORST MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 162: Oscillator Clock Monitor Reset
If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus COP reset is generated. The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 163 Mode to update the COP time-out period (CR[2:0]) and COP window (WCOP) setting loaded from NVM memory at reset release. Any value for the new COP time-out period and COP window setting is allowed MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 164: Power-On Reset (Por)
I bit CPMUINT (LOCKIE) Oscillator status I bit CPMUINT (OSCIE) interrupt Low voltage interrupt I bit CPMULVCTL (LVIE) High temperature I bit CPMUHTCTL (HTIE) interrupt Autonomous I bit CPMUAPICTL (APIE) Periodical Interrupt MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 165: Description Of Interrupt Operation
LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. 1. For details please refer to “4.4.6 System Clock Configurations” MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 166: Initialization/Application Information
COP configuration bits (WCOP,CR[2:0]) takes place which protects these bits from further accidental change In case of a program sequencing issue (code runaway) the COP configuration can not be accidentally modified anymore MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 167: Mc9S12Vrp Family Reference Manual Rev. 1.3 Nxp Semiconductors
(alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop Mode is entered. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 168 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 169: Introduction
The BDM includes these distinctive features: • Single-wire communication with host development system • Enhanced capability for allowing more flexibility in clock rates • SYNC command to determine communication rate • GO_UNTIL command MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 170: Modes Of Operation
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready to receive a new command. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 171: Block Diagram
(BDM soft reset) has occurred. Memory Map and Register Definition 5.3.1 Module Memory Map Table 5-2 shows the BDM memory map when BDM is active. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 172: Register Descriptions
CCR3 CCR2 CCR1 CCR0 0x3_FF07 Reserved 0x3_FF08 BDMPPR BPAE BPP3 BPP2 BPP1 BPP0 = Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 5-2. BDM Register Summary MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 173 (This does not apply in special single chip mode). — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 174 Flash EEPROM is configured for unsecure mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 175 BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed BPP[3:0] information regarding the program page window scheme, please refer to the device MMC description. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 176: Family Id Assignment
The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following 1. BDM is enabled and active immediately out of special single-chip reset. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 177: Bdm Hardware Commands
To distinguish between physical memory locations that share the same address, BDM memory resources are 1. This method is provided by the S12S_DBG module. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 178: Standard Bdm Firmware Commands
0x3_FF00–0x3_FFFF, and the CPU begins executing the standard BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 5-6. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 179: Bdm Command Structure
8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 180 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 5.4.6, “BDM Serial Interface” Section 5.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 181: Bdm Serial Interface
The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 182 The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 183 Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin 10 Cycles 10 Cycles Earliest Start of Next Bit Host Samples BKGD Pin Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 184: Serial Interface Hardware Handshake Protocol
If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 185 ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 186: Hardware Handshake Abort Procedure
The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 187 Electrical Conflict Speedup Pulse Host and Host Target Drive Drives SYNC to BKGD Pin To BKGD Pin Host SYNC Request Pulse BKGD Pin 16 Cycles Figure 5-13. ACK Pulse and SYNC Request Conflict MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 188 The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 189: Sync — Request Timed Reference Pulse
BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 190: Serial Communication Time Out
This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 191 The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 192 Background Debug Module (S12SBDMV1) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 193: Introduction
DUG: Device User Guide, describing the features of the device into which the DBG is integrated WORD: 16-bit data entity Data Line: 20-bit data entity CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 194: Overview
— Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 195: Modes Of Operation
CPU BUS MATCH CONTROL STATE LOGIC MATCH1 STATE SEQUENCER COMPARATOR B STATE MATCH2 COMPARATOR C TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 6-1. Debug Module Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 196: External Signal Description
COMPE 0x0028 DBGBCTL COMPE 0x0028 DBGCCTL COMPE 0x0029 DBGXAH Bit 17 Bit 16 0x002A DBGXAM Bit 15 Bit 8 0x002B DBGXAL Bit 7 Bit 0 Figure 6-2. Quick Reference to DBG Registers MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 197: Register Descriptions
ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 198 0x0027. See Table 6-4. Table 6-4. COMRV Encoding COMRV Visible Comparator Visible Register at 0x0027 Comparator A DBGSCR1 Comparator B DBGSCR2 Comparator C DBGSCR3 None DBGMFR 6.3.2.2 Debug Status Register (DBGSR) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 199 SSF[2:0] = 001. See Table 6-6 Table 6-6. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 Final State 101,110,111 Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 200 Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session. TALIGN 0 Trigger at end of stored data 1 Trigger before storing data Table 6-8. TRCMOD Trace Mode Bit Encoding TRCMOD Description Normal Loop1 Detail Compressed Pure PC MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 201 Figure 6-7. Debug Trace Buffer Register (DBGTB) Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 202 Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer contents. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 203 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 000001 64 lines valid, oldest data has been overwritten by most recent data 111110 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 204 DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 6-14. State Control Register Access Encoding COMRV Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 205 (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 206 The priorities described in Table 6-36 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 207 The priorities described in Table 6-36 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 208 Debug Comparator Control Register (DBGXCTL) The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 209 This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. (Comparators 0 Word access size is compared A and B) 1 Byte access size is compared MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 210 Table 6-23. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 211 Bit 8 Reset Figure 6-17. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 6-24 for visible register encoding. Write: If DBG not armed. See Table 6-24 for visible register encoding. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 212 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 6-19. Debug Comparator Data High Register (DBGADH) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 213 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 6-21. Debug Comparator Data High Mask Register (DBGADHM) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 214: Functional Description
A match with a comparator register value can initiate a state sequencer transition to another state (see Figure 6-24). Either forced or tagged matches are possible. Using MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 215: Comparator Modes
RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 216 Read accesses of ADDR[n] ADDR[n] LDAA #$BYTE ADDR[n] A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 217 Word No databus comparison $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match only data at ADDR[n+1] $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match only data at ADDR[n] $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data at ADDR[n] & ADDR[n+1] MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 218 In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The match condition requires that a valid MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 219: Match Modes (Forced Or Tagged)
CPU. It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 220: State Sequence Control
If a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 221: Trace Buffer Operation
Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 222 ; RTI Destination address TRACE BUFFER ENTRY 3 ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4 IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 STAB VAR_C1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 223 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored. Each Trace Buffer row consists of 2 information bits and 18 PC address bits MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 224 Bit 2 Bit 1 Bit 0 ADDR[17] ADDR[16] Figure 6-25. Field2 Bits in Detail Mode In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 225 6.4.5.4 Trace Buffer Organization (Compressed Pure PC mode) Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode) 2-bits 6-bits 6-bits 6-bits Line Mode Number Field 3 Field 2 Field 1 Field 0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 226 In compressed Pure PC mode on rollover the line with the oldest MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 227: Tagging
If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 228: Breakpoints
Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 229 Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 230: Application Information
Scenario 1 is possible with S12SDBGV1 SCR encoding 6.5.3 Scenario 2 A trigger is generated if a given sequence of 2 code events is executed. Figure 6-28. Scenario 2a SCR2=0101 SCR1=0011 Final State State2 State1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 231: Scenario 3
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 232 If no taghit points to final state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 233: Scenario 5
S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible. Figure 6-36. Scenario 7 SCR2=1100 SCR3=1101 SCR1=1101 Final State State3 State2 State1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 234: Scenario 8
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 235 Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 236 S12S Debug Module (S12DBGV2) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 237: Introduction
Term Meaning Condition Code Register (in the CPU) Interrupt Service Routine Micro-Controller Unit 7.1.2 Features • Interrupt vector base register (IVBR) • One spurious interrupt vector (at address vector base + 0x0080). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 238: Modes Of Operation
INT module. 1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 239: External Signal Description
This section describes in address order all the INT registers and their individual bits. 7.3.1.1 Interrupt Vector Base Register (IVBR) Address: 0x0120 IVB_ADDR[7:0] Reset Figure 7-2. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 240: Functional Description
CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 241: Reset Exception Requests
16 bits vector address based D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 242: Initialization/Application Information
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU. The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 243 1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 244 Interrupt Module (S12SINTV1) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 245: Introduction
Automatic return to low power after conversion sequence • Automatic compare with interrupt for higher than or less/equal than programmable value • Programmable sample time. • Left/right justified result data. • External trigger control. • Sequence complete interrupt. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 246 The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 247: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC12B12C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 248: Block Diagram
ATD 5 Successive ATD 6 Approximation ATD 7 ATD 8 Register (SAR) ATD 9 and DAC ATD 10 ATD 11 AN11 AN10 Sample & Hold Comparator Analog Figure 8-1. ADC12B12C Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 249: Signal Description
0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 8-2. ADC12B12C Register Summary (Sheet 1 of 3) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 250 Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0022 ATDDR9 Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 8-2. ADC12B12C Register Summary (Sheet 2 of 3) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 251 Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0026 ATDDR11 Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)” Unimple- 0x0028 - 0x002F mented = Unimplemented or Reserved Figure 8-2. ADC12B12C Register Summary (Sheet 3 of 3) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 252: Register Descriptions
The coding is summarized in Table 8-2. Table 8-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN11 AN11 AN11 AN11 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 253 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 8-5. Table 8-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data Reserved Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 254 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 8-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 255 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 8-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 256 Table 8-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 257 0.006 0.004 0.003 0.002 0.000 Table 8-10. Conversion Sequence Length Coding Number of Conversions per Sequence Table 8-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode Continue conversion MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 258 ------------------------------------ - Refer to Device Specification for allowed frequency range of f ATDCLK Table 8-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 259 AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN11 to AN0. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 260 Table 8-15. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN11 AN11 AN11 AN11 Internal_6, Temperature sense of ADC hardmacro Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 261 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 262 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 263 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 264 ATD Compare Higher Than Register (ATDCMPHT) Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Module Base + 0x000E CMPHT[11:0] Reset = Unimplemented or Reserved Figure 8-13. ATD Compare Higher Than Register (ATDCMPHT) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 265 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 266 ATDDRn. Table 8-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 267 ATDDRn. Table 8-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:8]=0000, Result-Bit[7:0] = conversion result 10-bit data Result-Bit[11:10]=00, Result-Bit[9:0] = conversion result MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 268: Functional Description
ATD module when a conversions is about to take place. The external trigger signal (out of reset ATD channel 11, configurable in ATDCTL1) is programmable to be MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 269 This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC12B12C. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 270: Resets
Table 8-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 8.3.2, “Register Descriptions” for further details. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 271: Introduction
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies • Programmable clock select logic 9.1.2 Modes of Operation There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 272: Block Diagram
Maximum possible channels, scalable in pairs from PWM0 to PWM7. Figure 9-1. Scalable PWM Block Diagram External Signal Description The scalable PWM module has a selected number of external pins. Refer to device specification for exact number. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 273: Pwm7 - Pwm0 — Pwm Channel 7 - 0
PCKA0 PWMCAE CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 PWMCTL CON67 CON45 CON23 CON01 PSWAI PFRZ = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 1 of 4) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 274 Bit 0 PWMCNT6 Bit 7 Bit 0 PWMCNT7 Bit 7 Bit 0 PWMPER0 Bit 7 Bit 0 = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 2 of 4) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 275 Bit 0 PWMDTY5 Bit 7 Bit 0 PWMDTY6 Bit 7 Bit 0 PWMDTY7 Bit 7 Bit 0 = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 3 of 4) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 276 While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts off for power savings. PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 Reset Figure 9-3. PWM Enable Register (PWME) Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 277 PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 278 Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 279 PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 280 Field Description 7–0 Center Aligned Output Modes on Channels 7–0 CAE[7:0] 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 281 PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 282 Each PWM channel has a choice of four clocks to use as the clock source for that channel as described below. PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 Reset Figure 9-9. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 283 PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 284 Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 285 Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. Section 9.4.2.3, “PWM Period and Duty” for more information. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 286 Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. Section 9.4.2.3, “PWM Period and Duty” for more information. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 287: Functional Description
SB. Each PWM channel has the capability of selecting one of four clocks, clock A, Clock B, clock SA or clock SB. The block diagram in Figure 9-15 shows the four different clocks and how the scaled clocks are created. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 288 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 289 PWM Ch 6 PCLK6 PCLKAB6 Clock to PWM Ch 7 PCLK7 PCLKAB7 Prescale Scale Clock Select Maximum possible channels, scalable in pairs from PWM0 to PWM7. Figure 9-15. PWM Clock Select Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 290 For channels 0, 1, 4, and 5 the clock choices are clock A. For channels 2, 3, 6, and 7 the clock choices are clock B. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 291: Pwm Channel Timers
PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 9.4.2.7, “PWM 16-Bit Functions” for more detail. NOTE The first PWM cycle after enabling the channel can be irregular. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 292 A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 9-16 and described in Section 9.4.2.5, “Left Aligned Outputs” Section 9.4.2.6, “Center Aligned Outputs”. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 293 9-16, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 9.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 294 PWMDTYx = 1 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 9-18. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 295 PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx PWMPERx PWMPERx Period = PWMPERx*2 Figure 9-19. PWM Center Aligned Output Waveform MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 296 When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in Figure 9-21. Similarly, when channels 4 and 5 are concatenated, channel 4 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 297 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 9-21. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 298 Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 299: Resets
All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured as an up counter out of reset. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 300: Interrupts
For channels 0, 1, 4, and 5 the clock choices are clock A. • For channels 2, 3, 6, and 7 the clock choices are clock B. Interrupts The PWM module has no interrupt. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 301: Introduction
IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 302: Features
Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 303: Block Diagram
RXEDG BERR Data Format Control Transmit TDRE Interrupt Transmit Transmit Control 1/16 Generation Baud Rate Generator Infrared Data Out TXD Transmit Shift Register Encoder SCI Data Register Figure 10-1. SCI Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 304: External Signal Description
10-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 305: Register Descriptions
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 10-2. SCI Register Summary MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 306 Note: . User should write SCIBD by word access. The updated SCIBD may take effect until next RT clock start, write SCIBDH or SCIBDL separately may cause baud generator load wrong data at that time,if second write later then RT clock. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 307 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 308 0 Even parity 1 Odd parity Table 10-4. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 309 If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 310 1 BERRIF interrupt requests enabled Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt BKDIE requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 311 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 10-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 10-19) Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 312 BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 313 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 314 (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 315 Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 316 In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 317: Functional Description
BKDIF Shift Register Break Detect BKDIE SCI Data BKDFE Register LIN Transmit BERRIF Collision SCTXD Detect BERRIE R16XCLK BERRM[1:0] Infrared Transmit Ir_TXD Encoder R32XCLK TNP[1:0] IREN Figure 10-14. Detailed SCI Block Diagram MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 318: Infrared Interface Submodule
LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 319: Data Format
(SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 10-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 320: Baud Rate Generation
.006 5208 76,804.9 4800.3 4,800 .006 10417 38,398.8 2399.9 2,400 .003 20833 19,200.3 1200.02 1,200 41667 9599.9 600.0 65535 6103.6 381.5 16x faster then baud rate divide 1/16 form transmit baud generator MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 321: Transmitter
TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 322 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 323 Does not change the framing error flag FE, parity error flag PE. • Does not clear the SCI data registers (SCIDRH/L) 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 324 TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 325 If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 326: Receiver
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 327 Table 10-17. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 328 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 10-19 summarizes the results of the stop bit samples. Table 10-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 329 RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 10-23. Start Bit Search Example 2 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 330 Perceived and Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 10-25. Start Bit Search Example 4 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 331 FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 332 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 333 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 334: Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 335: Loop Operation
NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same. 10.5 Initialization/Application Information 10.5.1 Reset Initialization Section 10.3.2, “Register Descriptions”. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 336: Modes Of Operation
Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred. IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 337 Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 338 Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 339: Recovery From Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode. 10.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 340 Serial Communication Interface (S12SCIV6) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 341: Introduction
Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 342: Block Diagrams
IOC1 - IOC0 — Input Capture and Output Compare Channel 1-0 Those pins serve as input capture or output compare for TIM16B2CV3 channel . NOTE For the description of interrupts see Section 11.6, “Interrupts”. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 343: Memory Map And Register Definition
EDG0B EDG0A TCTL4 0x000C R RESERV RESERV RESERV RESERV RESERV RESERV 0x000D RESERV TSCR2 0x000E R RESERV RESERV RESERV RESERV RESERV RESERV TFLG1 Figure 11-3. TIM16B2CV3 Register Summary (Sheet 1 of 2) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 344 Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description Input Capture or Output Compare Channel Configuration IOS[1:0] 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 345 Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes . MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 346 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits. This bit is writable only once out of reset. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 347 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reset Figure 11-10. Timer Control Register 1 (TCTL1) RESERVED RESERVED RESERVED RESERVED Reset Figure 11-11. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 348 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reset Figure 11-12. Timer Control Register 3 (TCTL3) RESERVED RESERVED RESERVED RESERVED EDG1B EDG1A EDG0B EDG0A Reset Figure 11-13. Timer Control Register 4 (TCTL4) Read: Anytime Write: Anytime. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 349 TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. 11.3.2.9 Timer System Control Register 2 (TSCR2) RESERVED Reset = Unimplemented or Reserved Figure 11-15. Timer System Control Register 2 (TSCR2) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 350 Figure 11-16. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 351 Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one . MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 352 Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. 11.3.2.13 Output Compare Pin Disconnect Register(OCPD) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED OCPD1 OCPD0 Reset Figure 11-20. Output Compare Pin Disconnect Register (OCPD) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 353 The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1 Table 11-17. Precision Timer Prescaler Selection Examples when PRNT = 1 Prescale PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Factor MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 354: Functional Description
PTPS2 PTPS1 PTPS0 Factor 11.4 Functional Description This section provides a complete functional description of the timer TIM16B2CV3 block. Please refer to the detailed timer block diagram in Figure 11-22 as necessary. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 355: Prescaler
2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 356: Input Capture
OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 357: Resets
Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 358 Timer Module (TIM16B2CV3) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 359: Introduction
Each driver has the following features: • Selectable gate control: HSDR[HSDRx] register bits or PWM or timer channels. • Open-load detection. • Slew rate control. • Over-current shutdown, comprising of: — Interrupt flag generation — Driver shutdown MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 360: Modes Of Operation
HSDRV2C module. The module consists of a control and an output stage. The high-side driver gate control can be routed. See PIM chapter for routing options. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 361: External Signal Description
Outputs of the two high-side drivers, intended to drive LEDs or resistive loads. 12.2.2 VSUPHS — High Side Driver Power Pin Power supply for the high-side driver. This pin must be connected to the main power supply with the appropriate reverse battery protection network. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 362: Memory Map And Register Definition
HSE1 HSE0 HSCR 0x0002 HSSLCU1 HSSLCU0 HSSLEN1 HSSLEN0 HSSLR 0x0003 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0004 Reserved HSOL1 HSOL0 0x0005 HSSR 0x0006 HSOCIE HSIE 0x0007 HSOCIF1 HSOCIF0 HSIF MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 363: Register Definition
HS_settling 12.3.4 HSDRV2C Configuration Register (HSCR) Module Base + 0x0001 Access: User read/write HSOCME1 HSOCME0 HSOLE1 HSOLE0 HSE1 HSE0 Reset = Unimplemented Figure 12-3. HSDRV2C Configuration Register (HSCR) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 364 1 High-side driver is enabled Note: After enabling the high-side driver (HSCR[HSEx]=1), a settling time t is required before the high-side HS_settling driver is allowed to be turned on (e.g. by writing to the HSDR). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 365: Hsdrv2C Slew Rate Control Register (Hsslr)
The voltage slew rate is limited for ~8 us when the associated driver is switched on to reduce the emission if the high-side driver is used as an off-board driver. These bits are only writable if the associated high-side driver is disabled (HSCR[HSEx]=0) 0 Slew rate control disabled 1 Slew rate contol enabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 366: Reserved Register
Table 12-7. Reserved Register Field Descriptions Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 367: Hsdrv2C Status Register (Hssr)
HLROLDT granted after enabling the high-load resistance open-load detection function in order to read valid data. 0 No open-load condition, I |I HLROLDC 1 Open-load condition, I I HLROLDC MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 368: Hsdrv2C Interrupt Enable Register (Hsie)
Write: Anytime Table 12-9. HSDRV Interrupt Enable Register (HSIE) Field Descriptions Field Description HSDRV2C Over-Current Interrupt Enable HSOCIE 0 Interrupt request is disabled 1Interrupt is requested whenever a HSIF[HSOCIFx] flag is set MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 369: Hsdrv2C Interrupt Flag Register (Hsif)
If the driving pin HS[x] stays at HVOLDC a voltage above an internal threshold then an open load will be detected for the associated high-side driver. The open-load condition is flagged in the HSDRV Status Register (HSSR). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 370: Over-Current Shutdown
HSDRV2C Over-Current Interrupt (HSOCI) HSOCIE = 1 If an over-current is detected the related interrupt flag HSOCIFx asserts. Depending on the setting of the HSDRV2C Error Interrupt Enable (HSOCIE) bit an interrupt is requested. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 371: Introduction
• Over-current protection with shutdown and interrupt while enabled • Active clamp to protect the device against over-voltage when the power transistor that is driving an inductive load (relay) is turned off. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 372: Modes Of Operation
LSDRV module. The module consists of a control and an output stage. Internal functions can be routed to control the low-side drivers. See PIM chapter for routing options. Figure 13-1. LSDRV Block Diagram LS0 control LSGND LS1 control MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 373: External Signal Description
Register Name 0x0000 LSDR1 LSDR0 LSDR 0x0001 LSOLE1 LSOLE0 LSE1 LSE0 LSCR 0x0002 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0003 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 374 Low-Side Drivers - LSDRV (S12LSDRV2) Table 13-3. Register Summary Address Offset Bit 7 Bit 0 Register Name 0x0004 Reserved LSOL1 LSOL0 0x0005 LSSR 0x0006 LSOCIE LSIE 0x0007 LSOCIF1 LSOCIF0 LSIF MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 375: Register Definition
Note: The low-side driver should be turned off (e.g. LSDR[LDSRn]=0 or OC=0 or PWM=0) and the load should be de-energized before going into Stop Mode or disabling the low-side driver with the LSCR[LSEn] bits. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 376: Lsdrv Configuration Register (Lscr)
Note: After enabling the low-side driver (write “1” to LSCR[LSEn]) a settling time t is required before the LS_settling low-side driver is allowed to be turned on (e.g. by writing LSDR[LSDRn] bits). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 377: Reserved Register
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 378: Lsdrv Status Register (Lssr)
HLROLDT order to read valid data. I 0 Open-load condition I HLROLDC I 1 Open-load condition I HLROLDC MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 379: Lsdrv Interrupt Enable Register (Lsie)
Read: Anytime Write: Anytime Table 13-9. LSIE Register Field Descriptions Field Description LSDRV Error Interrupt Enable LSOCIE 0 Interrupt request is disabled 1 Interrupt will be requested whenever a LSOCIFx flag is set MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 380: Lsdrv Interrupt Flag Register (Lsif)
PIM module. 0 No over-current event occurred since last clearing of flag 1 An over-current event occurred since last clearing of flag MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 381: Functional Description
Entering and exiting MCU stop mode has no effect on the interrupt flags. Table 13-11 lists all interrupt sources of the LSDRVmodule. Vector addresses and interrupt priorities are defined at MCU level. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 382 LSDRV Over Current Interrupt (LSOCI) If a low-side driver over-current event is detected the related interrupt flag LSIF[LSOCIFn] asserts. Depending on the setting of the LSDRV Error Interrupt Enable (LSIE[LSOCIE]) bit an interrupt is requested. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 383: Introduction
(LS2DR) was chosen as source in PIM module, then the respective low-side driver stays turned off until the software sets the data register (LS2DR). When the timer or PWM were chosen MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 384: Block Diagram
LS2DRV module. The module consists of a control and an output stage. Internal functions can be routed to control the low-side drivers. See PIM chapter for routing options. Figure 14-1. LS2DRV Block Diagram LS control Low Side Driver Control VSSX MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 385: External Signal Description
Table 14-3. Register Summary Address Offset Bit 7 Bit 0 Register Name 0x0000 LS2DR LS2DR 0x0001 LS2E LS2CR 0x0002 Reserved 0x0003 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0004 Reserved 0x0005 Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 386 Low-Side Driver - LS2DRV (S12LS2DRV_V1) Table 14-3. Register Summary Address Offset Bit 7 Bit 0 Register Name 0x0006 LS2OCIE LS2IE 0x0007 LS2OCIF LS2IF MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 387: Register Definition
1 Low-side driver is turned on NOTE After enabling the low-side driver with the LS2E bit in LS2CR register, the user must wait a minimum settling time t LS2_settling before turning on the low-side driver. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 388: Ls2Drv Configuration Register (Ls2Cr)
NOTE After enabling the low-side driver (write “1” to LS2E) a settling time t is required before the low-side driver is allowed LS_settling to be turned on (e.g. by writing LS2DR bits). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 389: Reserved Register
Writing to this register when in special mode can alter the module’s functionality. Table 14-6. Reserved Register Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 390: Ls2Drv Interrupt Enable Register (Ls2Ie)
Read: Anytime Write: Anytime Table 14-7. LS2IE Register Field Descriptions Field Description LS2DRV Error Interrupt Enable LS2OCIE 0 Interrupt request is disabled 1 Interrupt will be requested whenever a LS2OCIFx flag is set MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 391: Ls2Drv Interrupt Flag Register (Ls2If)
Once these flags are cleared, the related driver is again driven by the source selected in PIM module. 0 No over-current event occurred since last clearing of flag 1 An over-current event occurred since last clearing of flag MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 392: Functional Description
LS2DRV Over Current Interrupt (LSOCI) If a low-side driver over-current event is detected the related interrupt flag LS2OCIF asserts. Depending on the setting of the LS2DRV Error Interrupt Enable (LS2OCIE) bit an interrupt is requested. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 393: Features
The ISENSE module functions as follows in the system power modes: • In run mode all features are available. • In wait mode all features are available. • In stop mode the ISENSE module is disabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 394: Block Diagram
AMP — Current Sense Amplifier Output Pin This pin is the output of the current sense amplifier. At the MCU level this pin is shared with an ADC channel. For ADC channel assignment see MCU pin out section. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 395: Memory Map And Register Definition
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 396 Current Sense Interrupt Enable Register (CSIE) 15.5.2.2 Module Base + 0x0001 Access: User read write OCIE Reset = Unimplemented Figure 15-4. Current Sense Interrupt Enable Register (CSIE) 1. Read: Anytime Write: Anytime MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 397 Table 15-3. CSIE Register Field Descriptions Field Description Over Current Interrupt Enable — This bit enables over current interrupt. OCIE 0 Over current interrupt OCIF is disabled. 1 Over current interrupt OCIF is enabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 398 . The status flag is cleared by hardware if the output voltage of the current sense amplifier is less than the threshold voltage V 0 Current sense amplifier output voltage is less than V 1 Current sense amplifier output voltage is greater than V MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 399 15.5.2.6 Module Base + 0x0005 Access: User read/write OCT[4:0] Reset = Unimplemented Figure 15-8. Current Sense Over Current Threshold Register (OCT) 1. Read: Anytime Write: Write protected bits OCT only if CSWP=1 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 400: Functional Description
OFFS[2:0] bits. The output of the current sense amplifier is connected to the positive input of the over current comparator. The negative input is MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 401 Figure 15-9. Current Sense Amplifier Connected as Differential Amplifier OCT[4:0] Over Current Condition > V sense 6 bit OFFS[2:0] Output Voltage to ADC AMPP = a V sense offset AMPM sense sense MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 402: Interrupts
Current Sense Amplifier Module (ISENSEV1) 15.6.2 Interrupts In case of an over current condition the over current interrupt flag CSIF[OCIF] asserts. This flag generates an interrupt if the enable bit CSIE[OCIE] is set. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 403: Introduction
A selectable internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. To be used as a master node, an external MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 404: Modes Of Operation
LIN Physical Layer. The module consists of a receiver with wake-up control, a transmitter with slope and timeout control, a current sensor with overcurrent protection as well as a registers control block. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 405 & % + " #$ - , * . * * * Figure 16-1. LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 406: External Signal Description
In standby mode this output is disabled, and sends only a short pulse in case the wake-up functionality is enabled and a valid wake-up pulse was received in the LIN Bus. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 407: Memory Map And Register Definition
Reserved Reserved 0x0003 LPDTDIS LPSLR1 LPSLR0 LPSLRM 0x0004 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0x0005 LPSR 0x0006 LPDTIE LPOCIE LPIE 0x0007 LPDTIF LPOCIF LPIF Figure 16-2. Register Summary MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 408: Register Descriptions
The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM chapter of the device Reference Manual for more info. Port LP Data Bit 0 — Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time. LPDR0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 409 LIN Pullup Resistor Enable — Selects pullup resistor. LPPUE 0 The pullup resistor is high ohmic (330 k). 1 The 34 k pullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 410 LIN Slew Rate Mode Register (LPSLRM) Module Base + Address 0x0003 Access: User read/write LPDTDIS LPSLR1 LPSLR0 Reset = Unimplemented Figure 16-6. LIN Slew Rate Mode Register (LPSLRM) Read: Anytime Write: Only in shutdown mode (LPE=0) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 411 Table 16-6. Reserved Register Field Description Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 412 LPTDIF is set again after attempting to clear it. 0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout. 1 LPTxD is still dominant after a TxD-dominant timeout. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 413 0 Interrupt request is disabled. 1 Interrupt is requested if LPDTIF bit is set. LIN transmitter Overcurrent Interrupt Enable — LPOCIE 0 Interrupt request is disabled. 1 Interrupt is requested if LPOCIF bit is set. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 414 If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see16.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 415: Functional Description
A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 416: Modes
If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 417 SCI interrupt, then the SCI interrupt will execute first). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 418 # $ " ! " ! % % ! " ! " ! # $ " ! Figure 16-11. LIN Physical Layer Mode Transitions MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 419: Interrupts
2 IRC periods (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 16-12 shows the different scenarios for overcurrent interrupt handling. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 420 To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 421 ! "! ! ! # ! "! ! ! "! Figure 16-13. TxD-dominant timeout interrupt handling MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 422: Application Information
— If the receiver must remain enabled, set the LIN Physical Layer into receive only mode instead. 2. Do all required configurations (SCI, etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 423 7. Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the ISR will be called again. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 424 LIN Physical Layer (S12LINPHYV2) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 425: Introduction
BSESE takes precedence over BSUSE. BSEAE takes precedence over BSUAE. 2. Stop mode During stop mode operation the path from the VSENSE pin through the resistor chain to ground is opened and the low voltage sense features are disabled. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 426: Block Diagram
This pin can be connected to the supply (Battery) line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 427: Vsup — Voltage Supply Pin
Memory Map and Register Definition This section provides the detailed information of all registers for the BATS module. 17.3.1 Register Summary Figure 17-2 shows the summary of all implemented registers inside the BATS module. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 428: Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 429 BATS VSENSE Level Sense Enable — This bit connects the VSENSE pin through the resistor chain to ground BSESE and enables the Voltage Level Sense features measuring BVLC and BVHC.Setting this bit will clear bit BSUSE 0 Level Sense features disabled 1 Level Sense features enabled MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 430 + two bus cycles the measured EN_UNC value is invalid. This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 431 V (falling edge) or V (rising edge) measured LBI_A measured LBI_D V V (falling edge) or V (rising edge) measured LBI_A measured LBI_D Figure 17-5. BATS Voltage Sensing HBI_A HBI_D LBI_D LBI_A MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 432 BATS Interrupt Flag Register (BATIF) 17.3.2.4 Module Base + 0x0003 Access: User read/write BVHIF BVLIF Reset = Unimplemented Figure 17-7. BATS Interrupt Flag Register (BATIF) Read: Anytime Write: Anytime, write 1 to clear MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 433: Functional Description
Analog to Digital Converter Channel. Also the BATS module can be configured to generate a low and high voltage interrupt based on VSENSE or VSUP. The trigger level of the high and low interrupt are selectable. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 434: Interrupts
(rising edge) measure LBI3_A measure LBI3_D or when d) V selected with BVLS[1:0] = 0x3 LBI4 V V at selected pin V (falling edge) or V (rising edge) measure LBI4_A measure LBI4_D MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 435 Voltage Interrupt flag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI). MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 436 Supply Voltage Sensor - (BATSV2) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 437: Chapter 18
Chapter 18 64 KByte Flash Module (S12FTMRG64K4KV2) Table 18-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V02.00 25 Feb 2016 Initial version MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 438: Introduction
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 439: Features
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 18.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 18-1. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 440: External Signal Description
Clock Clock Divider FCLK Memory Controller D-Flash 2Kx22 sector 0 sector 1 sector 15 Figure 18-1. FTMRG64K4K Block Diagram 18.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 441: Memory Map And Registers
0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 442 Section 18.3.2.2, “Flash Security Register (FSEC)” 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 443 Protection Fixed End Flash Protected/Unprotected Higher Region 0x3_E000 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 Flash Configuration Field P-Flash END = 0x3_FFFF 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 18-2. P-Flash Memory Map MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 444 0x0_4200 – 0x0_57FF Reserved 0x0_5800 – 0x0_59FF Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 18.4.3 for NVMRES (NVM Resource) detail. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 445: Register Descriptions
Address & Name FDIVLD FCLKDIV FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 FSEC FCCOBIX CCOBIX2 CCOBIX1 CCOBIX0 Figure 18-4. FTMRG64K4K Register Summary MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 446 DPS2 DPS1 DPS0 FCCOBHI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBLO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FRSV1 FRSV2 FRSV3 FRSV4 FOPT Figure 18-4. FTMRG64K4K Register Summary (continued) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 447 Table 18-7. FCLKDIV Field Descriptions Field Description Clock Divider Loaded FDIVLD 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 448 BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. 18.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 449 ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. Table 18-11. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED Preferred SEC state to set MCU to secured state. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 450 All bits in the FRSV0 register read 0 and are not writable. 18.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 451 The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. DFDIE SFDIE Reset = Unimplemented or Reserved Figure 18-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 452 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 453 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 454 Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area FPHS[1:0] in P-Flash memory as shown inTable 18-19. The FPHS bits can only be written to while the FPHDIS bit is set. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 455 Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 456 64 KByte Flash Module (S12FTMRG64K4KV2) Normal Single Chip Mode while providing as much protection as possible if reprogramming is not required. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 457 FLASH START 0x3_8000 0x3_FFFF Scenario FLASH START 0x3_8000 0x3_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 458 During the reset sequence, fields DPOPEN and DPS of the DFPROT register are loaded with the contents of the D-Flash protection byte in the Flash configuration field at global address 0x3_FF0D located in MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 459 2816 bytes 1011 0x0_0400 – 0x0_0FFF 3072 bytes 1100 0x0_0400 – 0x0_10FF 3328 bytes 1101 0x0_0400 – 0x0_11FF 3584 bytes 1110 0x0_0400 – 0x0_12FF 3840 bytes 1111 0x0_0400 – 0x0_13FF 4096 bytes MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 460 Table 18-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command 6’h0, Global address [17:16] Global address [15:8] Global address [7:0] Data 0 [15:8] Data 0 [7:0] MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 461 = Unimplemented or Reserved Figure 18-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 18.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 462 Figure 18-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 463 18.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. Reset = Unimplemented or Reserved Figure 18-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 464: Functional Description
BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 465 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 18-26. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 466 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 18-26. Generic Flash Command Write Sequence Flowchart MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 467 0x11 Program D-Flash 0x12 Erase D-Flash Sector Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. Secured Normal Single Chip mode. Secured Special Single Chip mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 468 Table 18-29. D-Flash Commands FCMD Command Function on D-Flash Memory Erase Verify All Verify that all D-Flash (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the D-Flash block is erased. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 469: Allowed Simultaneous P-Flash And D-Flash Operations
‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 18.4.6.12 Section 18.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 470: Flash Command Description
Set if any errors have been encountered during the read or if blank check failed. Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 471 The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 472 FCCOB Parameters 0x04 Not Required Read Once phrase index (0x0000 - 0x0007) Read Once word 0 value Read Once word 1 value Read Once word 2 value Read Once word 3 value MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 473 The CCIF flag will set after the Program P-Flash operation has completed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 474 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 475 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 18.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 476 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 477 The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 18-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 478 The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or D-Flash block. Table 18-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Flash block selection code [1:0] 0x0D Table 18-34 Margin level setting. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 479 User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 480 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 0x0003 Field Margin-1 Level 0x0004 Field Margin-0 Level Read margin to the erased state Read margin to the programmed state MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 481 D-Flash memory is erased. The CCIF flag will set after the Erase Verify D-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 482 Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program D-Flash command launch determines how many words will be programmed in the D-Flash block. The CCIF flag is set when the operation has completed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 483 Set if the selected area of the D-Flash memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 484: Interrupts
The logic used for generating the Flash module interrupts is shown in Figure 18-27. CCIE Flash Command Interrupt Request CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 18-27. Flash Module Interrupts Implementation MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 485: Wait Mode
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 486: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state 8. Reset the MCU MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 487: Mode And Security Effects On Flash Command Availability
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 488 64 KByte Flash Module (S12FTMRG64K4KV2) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 489: A.1 General
5V power supply output for I/O drivers generated by on chip voltage regulator VSSX1 Ground pin for I/O drivers VDDX2 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator VSSX2 Ground pin for I/O drivers MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 490: A.1.2 Pins
Px is greater than V a positive injection current I will flow through diode D1 into VDDX node. If this injection current I is greater than I , the internal power Load MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 491: A.1.4 Absolute Maximum Ratings
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level. Table A-3. Absolute Maximum Ratings Rating Symbol Unit Voltage regulator supply voltage –0.3 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 492: A.1.5 Esd Protection And Latch-Up Immunity
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 493 ESDIEC LIN vs LGND Latch-up Current of 5V GPIO’s at T=125 C positive +100 negative -100 Latch-up Current for LS[2:0], HS[1:0], VSENSE, LIN & HVI[5:0] at T=125 C positive +100 negative -100 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 494: A.1.6 Recommended Capacitor
–40 — C Operating junction temperature range –40 — Operating ambient temperature range (option V) –40 — C Operating junction temperature range –40 — Operating ambient temperature range (option M) –40 — MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 495: A.1.8 Power Dissipation And Thermal Characteristics
EVDD GPIO Table A-8. Power Dissipation Components Power Component Description Internal Power through VSUP pin, which is double PHS0/1 bonded to VSUP pad and VSUPHS pad. Power dissipation of High-side drivers DSONHS MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 496 MCU power dissipation P Figure A-2. Supply Currents Overview S12VRP PLS0/1 SENSE VBAT VBAT LS[2:0] VSENSE VSUP/ VSUPHS PHS0/1 VDDA HS[1:0] VDDX1 VDDX2 Switch HVI[5:0] Inputs VSSX1 GPIO VSSX2 EVDD EVDD MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 497: A.2 General Purpose I/O Characteristics
— — +0.3 Input low voltage — — 0.35*V Input low voltage –0.3 — — Input hysteresis — — Input leakage current (pins in high impedance input A — mode) or V MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 498 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. Refer to Section A.1.3, “Current Injection” for more details MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 499 1/f RESET pin input pulse filtered — — P_MASK RESET pin input pulse passed — — P_PASS Parameter only applies in stop or pseudo stop mode. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 500: A.2.1 High Voltage Inputs (Hvi) Characteristics
IRC1M trimmed to 1MHz. The bus clock frequency is set to the max value of 25MHz and the CPU frequency is 50 MHz. Table A-13, Table A-14 Table A-15 show the configuration of the CPMU module and the peripherals for Run, Wait and Stop current measurement. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 501 Configured to toggle all pins at the rate of 40kHz The peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on a single input channel he module is disabled as in final applications MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 502 . Die self heating due to stop current can be ignored. Table A-18. Pseudo Stop Current Characteristics Conditions are: V =12V, API, COP & RTI enabled Rating Symbol Unit A = 25C SUPPS MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 503: B.1 Vreg Electrical Specifications
For the given maximum load currents and V input voltages, the MCU will stay out of reset. Please note that the core current is derived from VDDX Further limitation may apply due to maximum allowable T MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 504: B.2 Reset And Stop Timing Characteristics
Table B-2. Reset and Stop Timing Characteristics Characteristic Symbol Typical Unit Startup from Reset (normal mode) — STARTUP Startup from Reset (special mode) — STARTUP s Recovery time from STOP — — STP_REC Finals values subject to confirmation. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 505: B.3 Osc Electrical Specifications
VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-1. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 506 ------------------------------------------------ - N POSTDIV J(N) Figure B-2. Maximum Bus Clock Jitter Approximation NOTE On timers and serial modules a pre-scaler will eliminate the effect of the jitter to a large extent. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 507 PLL Clock Monitor Failure assert frequency 0.45 PMFA % deviation from target frequency = 1MHz (IRC), f = 25MHz equivalent f =50MHz, CPMUSYNR=0x58, CPMUREFDIV=0x00, CPMUPOSTDIV=0x00 = 4MHz (XOSCLCP), f = 24MHz equivalent f =48MHz, CPMUSYNR=0x05, CPMUREFDIV=0x40, CPMUPOSTDIV=0x00 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 508: C.1 Adc Operating Characteristics
AD pins because the output drivers are supplied from the VDDA/VSSA ADC supply pins. Although internal design measures are implemented to minimize the affect of output driver noise, it MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 509 4. Similarly, when the ADC is converting an HVI pin voltage, then the impedance converter bypass must be disabled to ensure that current injection on PADx pins does not impact the HVI ADC conversion result. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 510 Disruptive analog input current -2.5 — Coupling ratio positive current injection — — 1E-4 Coupling ratio negative current injection — — 5E-3 1 Refer to Section C.1.1.2 Source Resistance for further information concerning source resistance MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 511: C.2 Adc Analog Input Parasitics
Leakage current is guaranteed by specification. =130 jmax Figure C-1. ADC input parasitics ADC Accuracy Table C-3 specifies the ADC conversion performance excluding any errors due to current injection, input capacitance and source resistance. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 512: C.3.1 Adc Accuracy Definitions
------------------------- - 1 – 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: – INL n DNL i ------------------ - n – 1LSB MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 513 $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 95 100 105 110 115 120 5000 + Figure C-2. ADC Accuracy Definitions MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 514 8-Bit counts 1 Absolute Error 8-Bit -1.5 counts ADC values are characterized over the range 4.5 V < V < 5.5 V. Production test uses 4.85 V < V < 5.15 V. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 515: D.1 Static Characteristics
< 150°C – LEAK_H Open Load Detection disabled (0V< V < V HS0/1 SUP_HS A High-Load Resistance Open-Load Detection Current – – HLROLDC (if High-side driver is enabled and gate turned off) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 516: D.2 Dynamic Characteristics
– HLROLDT (capacitive load = 50pF) High side driver internal falling delay time HSDintDelay90 = 300 s – 2.98 – load s = 5 k – 3.97 – Measuring Condition: 90% MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 517: E.1 Static Electrical Characteristics
<5.5V, characterization showed that all parameters generally stay within the indicated specification. LINSUP The V voltage is provided by the VLINSUP supply. This supply mapping is described in device level LINSUP documentation. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 518: E.2 Dynamic Electrical Characteristics
-40°C < TJ < 150°C Duty cycle 3 0.417 — — = 0.778 x V HRec(max) LINSUP = 0.616 x V HDom(max) LINSUP = 5.5V...18V LINSUP = 96us D3 = t / (2 x t Bus_rec(min) MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 519 D2 and D4 which may increase and potentially go beyond their maximum limits for highly loaded buses. The V voltage is provided by the VLINSUP supply. This supply mapping is described in device level LINSUP documentation. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 520: F.1 Lsdrv Static Characteristics
– LEAK_L Open Load Detection disabled. A Leakage Current -40°C < T < 150°C – – LEAK_H Open Load Detection disabled. Active Output Voltage Clamp (I = 150 mA) – PLS0/1 CLAMP MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 521: F.2 Lsdrv Dynamic Characteristics
T = 25°C under nominal conditions unless otherwise noted. Ratings Symbol Output low voltage — — Maximum allowed continuous current — Over-current Detect Threshold A Leakage Current – LEAK_H MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 522: G.1 Operating Characteristics
Current Sense Amplifier large signal settling time — — cslsst s Over Current Comparator filter time constant Over Current Comparator threshold tolerance — OCCtt Output current range for which the effective output resistance specification applies MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 523: H.1 Static Electrical Characteristics
5.5V < VSUP < 29 V Analog Input Matching Matching Absolute Error on V - compared to V / Ratio – +-2% +-5% – SENSE VSENSE - compared to V / Ratio VSUP MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 524: H.2 Dynamic Electrical Characteristics
150°C unless otherwise noted. Typical values reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted. Ratings Symbol Unit s Enable Uncertainty Time – – EN_UNC Voltage Warning Low Pass Filter – – VWLP_filter MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 525: I.1 Nvm Timing Parameters
All timing parameters are a function of the bus clock frequency, f . All program and erase times NVMBUS are also a function of the NVM operating frequency, f . A summary of key timing parameters can NVMOP be found in Table I-1. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 526 Maximum times are based on typical f and typical f plus aging NVMOP NVMBUS Worst times are based on minimum f and minimum f plus aging NVMOP NVMBUS Affected by Pflash size Affected by Dflash size MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 527: I.2 Nvm Reliability Parameters
25C using the Arrhenius equation. For additional information on how NXP defines Typical Data Retention, please refer to Engineering Bulletin EB618 Spec table quotes typical endurance evaluated at 25C for this product family. For additional information on how NXP defines Typical Endurance, please refer to Engineering Bulletin EB619. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 528 NVM Electrical Parameters MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 529: Appendix J
Appendix J Package Information MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 530: Package Information
Package Information MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 531: Package Information
Package Information MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 532: Package Information
Package Information MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 533: Appendix K
/ mask-independent partnumber and the mask set number. NOTE Not every combination is offered. The mask identifier suffix and the Tape & Reel suffix are always both omitted from the partnumber which is actually marked on the device. MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 534: Ordering Information
S12: S12-16-Bit MCU-core V: indicates part of the MagniV Series Main Memory Type: 9 = Flash Status / Partnumber S or SC = Maskset specific partnumber MC = Generic, mask independent partnumber MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 535: L.1 0X0000-0X0009 Port Integration Module (Pim) Map 1 Of 4
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x000C PUCR BKPUE PDPEE 0x000D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 536: L.4 0X000E-0X000F Reserved
PIX3 PIX2 PIX1 PIX0 0x0016 Reserved 0x0017 Reserved 0x0018-0x0019 Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0018 Reserved 0x0019 Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 537: L.7 0X001A-0X001B Part Id Registers
0x0024 DBGTBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0025 DBGTBL 0x0026 DBGCNT 0x0027 DBGSCRX 0x0027 DBGMFR 0x0028 DBGACTL COMPE 0x0028 DBGBCTL COMPE MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 538: L.10 0X0030-0X0033 Reserved
0x0034-0x003F Clock Reset and Power Management (CPMU) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0034 CPMUSYNR VCOFRQ[1:0] SYNDIV[5:0] 0x0035 CPMUREFDIV REFFRQ[1:0] REFDIV[3:0] CPMUPOSTDI 0x0036 POSTDIV[4:0] MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 539: L.12 0X0040-0X006F Timer Module (Tim0) Map
Reserved Reserved TOV1 TOV0 0x0048 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0049 TIM0TCTL2 Reserved Reserved Reserved Reserved 0x004A Reserved 0x004B TIM0TCTL4 Reserved Reserved Reserved Reserved EDG1B EDG1A EDG0B EDG0A MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 540: L.13 0X0070-0X009F Analog To Digital Converter (Atd) Map
0x0072 ATDCTL2 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE 0x0073 ATDCTL3 FIFO FRZ1 FRZ0 0x0074 ATDCTL4 SMP2 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 0x0075 ATDCTL5 SCAN MULT 0x0076 ATDSTAT0 ETORF FIFOR MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 541 Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0094 ATDDR10 Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 8.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0096 ATDDR11 Section 8.3.2.12.2, “Right Justified Result Data (DJM=1)” 0x0098- Reserved 0x009F MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 542: L.14 0X00A0-0X00C7 Pulse Width Modulator 6-Channels (Pwm) Map
0x00B0 PWMCNT4 Bit 7 Bit 0 0x00B1 PWMCNT5 Bit 7 Bit 0 0x00B2 PWMCNT6 Bit 7 Bit 0 0x00B3 PWMCNT7 0x00B4 PWMPER0 Bit 7 Bit 0 0x00B5 PWMPER1 Bit 7 Bit 0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 543: L.15 0X00C8-0X00Cf Serial Communication Interface (Sci0) Map
SBR12 SBR11 SBR10 SBR9 SBR8 0x00C9 SCI0BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x00CA SCI0CR1 LOOPS SCISWAI RSRC WAKE 0x00C8 SCI0ASR1 RXEDGIF BERRV BERRIF BKDIF 0x00C9 SCI0ACR1 RXEDGIE BERRIE BKDIE MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 544 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 545: L.16 0X00D0-0X00D7 Serial Communication Interface (Sci1) Map
FDIV3 FDIV2 FDIV1 FDIV0 R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0101 FSEC 0x0102 FCCOBIX CCOBIX2 CCOBIX1 CCOBIX0 0x0103 FRSV0 0x0104 FCNFG CCIE IGNSF FDFD FSFD 0x0105 FERCNFG DFDIE SFDIE MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 546: L.18 0X0120 Interrupt Vector Base Register
FRSV5 0x0112 FRSV6 0x0113 FRSV7 L.18 0x0120 Interrupt Vector Base Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0120 IVBR IVB_ADDR[7:0] MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 547: L.19 0X0140-0X0147 High Side Drivers (Hsdrv2C)
LSOCIF1 LSOCIF0 L.21 0x0158-0x015F Low Side Driver (LS2DRV) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0158 LS2DR LS2DR 0x0159 LS2CR LS2E MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 548: L.22 0X0170-0X0177 Supply Voltage Sense (Bats)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0170 BATE BVHS BVLS[1:0] BSUAE BSUSE BSEAE BSESE BVHC BVLC 0x0171 BATSR 0x0172 BATIE BVHIE BVLIE MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... -
Page 549: L.23 0X0178-0X017F Current Sense Amplifier (Isense)
Reserved Reserved Reserved IOS1 IOS0 0x0181 TIM1CFORC Reserved Reserved Reserved Reserved Reserved Reserved FOC1 FOC0 0x0182- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0183 Bit 15 Bit 8 0x0184 TIM1TCNTH MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 550 OCPD1 OCPD0 0x01AD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x01AE TIM1PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0x01AF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 551: L.25 0X0240 -0X027F Port Integration Module (Pim) Map 4 Of 4
DDRT1 DDRT0 0x0243 Reserved 0x0244 PERT PERT3 PERT2 PERT1 PERT0 0x0245 PPST PPST3 PPST2 PPST1 PPST0 0x0246 MODRR0 LS2RR1 LS2RR0 LS1RR1 LS1RR0 LS0RR1 LS0RR0 0x0247 MODRR1 PWM5ET1 PWM4ET0 HS1RR1 HS1RR0 HS0RR1 HS0RR0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 552 0x0265 PTAENL PTAENL5 PTAENL4 PTAENL3 PTAENL2 PTAENL1 PTAENL0 0x0266 PTADIRL PTADIRL5 PTADIRL4 PTADIRL3 PTADIRL2 PTADIRL1 PTADIRL0 PTABYPL PTABYPL PTABYPL PTABYPL PTABYPL PTABYPL 0x0267 PTABYPL 0x0268 PTPSL PTPSL5 PTPSL4 PTPSL3 PTPSL2 PTPSL1 PTPSL0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
- Page 553 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 0x027A Reserved 0x027B PPS1AD PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 0x027C Reserved 0x027D PIE1AD PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 0x027E Reserved 0x027F PIF1AD PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors...
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Page 554: L.26 0X02F0-0X02Ff Clock And Power Management Unit (Cpmu) Map 2 Of 2
0x02F7 CPMUHTTR HTOE HTTR3 HTTR2 HTTR1 HTTR0 CPMU 0x02F8 TCTRIM[3:0] IRCTRIM[9:8] IRCTRIMH CPMU 0x02F9 IRCTRIM[7:0] IRCTRIML 0x02FA CPMUOSC OSCE 0x02FB CPMUPROT PROT 0x02FC Reserved 0x02FD Reserved 0x02FE CPMUOSC2 OMRE OSCMOD 0x02FF Reserved MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors... - Page 555 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right Home Page: to make changes without further notice to any products herein.
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