Debug Comparator C Extension Register (Dbg_Ccx) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and registers

28.3.11 Debug Comparator C Extension Register (DBG_CCX)

All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + Ah offset = 18CAh
Bit 7
Read
RWCEN
Write
Reset 0
Field
7 Read/Write Comparator C Enable Bit
RWCEN
The RWCEN bit controls whether read or write comparison is enabled for Comparator C.
0 Read/Write is not used in comparison.
1 Read/Write is used in comparison.
6 Read/Write Comparator C Value Bit
RWC
The RWC bit controls whether read or write is used in compare for Comparator C. The RWC bit is not
used if RWCEN = 0.
0 Write cycle will be matched.
1 Read cycle will be matched.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
560
NOTE
6 5
RWC
0 0
DBG_CCX field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0
0 0
Description
2 1
0 0
NXP Semiconductors
0
0