Memory Map And Register Description - NXP Semiconductors MC9S08SU16 Reference Manual

the end of the pipe, the CPU executes a BGND instruction to go to active background
mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU
to finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial
WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI
instruction instead of going to active background mode.

27.4 Memory map and register description

This section contains the descriptions of the BDCand DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet
for the absolute address assignments for all DBG registers. This section refers to registers
and control bits only by their names. An NXP-provided equate or header file is used to
translate these names into the appropriate absolute addresses.
Absolute
address
(hex)
0 BDC Status and Control Register (BDC_SCR)
1 BDC Breakpoint Match Register: High (BDC_BKPTH)
2 BDC Breakpoint Register: Low (BDC_BKPTL)
System Background Debug Force Reset Register
3
(BDC_SBDFR)
27.4.1 BDC Status and Control Register (BDC_SCR)
This register can be read or written by serial BDC commands (READ_STATUS and
WRITE_CONTROL) but is not accessible to user programs because it is not located in
the normal memory map of the MCU.
The reset values shown in the register figure are those in the
normal reset conditions. If the MCU is reset in BDM, ENBDM,
BDMACT, CLKSW will be reset to 1 and others all be to 0.
NXP Semiconductors
BDC memory map
Register name
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 27 Development support
Width
Access Reset value
(in bits)
8 R/W 00h
8 R/W 00h
8 R/W 00h
W
8 (always 00h
reads 0)
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