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The target, upon detecting the SYNC request from the host (which is a much longer low
time than would ever occur during normal BDC communications):
• Waits for BKGD to return to a logic high
• Delays 16 cycles to allow the host to stop driving the high speedup pulse
• Drives BKGD low for 128 BDC clock cycles
• Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
• Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the
correct speed for subsequent BDC communications. Typically, the host can determine the
correct communication speed within a few percent of the actual target speed and the
communication protocol can easily tolerate speed errors of several percent.
27.2.4 BDC hardware breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU
address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can
generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU
to enter active background mode at the first instruction boundary following any access to
the breakpoint address. The tagged breakpoint causes the instruction opcode at the
breakpoint address to be tagged so that the CPU will enter active background mode rather
than executing that instruction if and when it reaches the end of the instruction queue.
This implies that tagged breakpoints can be placed only at the address of an instruction
opcode while forced breakpoints can be set at any address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register
(BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0,
its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are
requested regardless of the values in other BDC breakpoint registers and control bits. The
force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged
(FTS = 0) type breakpoints.
The on-chip debug module (DBG) includes circuitry for two additional hardware
breakpoints that are more flexible than the simple breakpoint in the BDC module.
27.3 On-chip debug system (DBG)
Because HCS08 devices do not have external address and data buses, the most important
functions of an in-circuit emulator have been built onto the chip with the MCU. The
debug system consists of an 8-stage FIFO that can store address or data bus information,
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 27 Development support
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