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Functional Description
MODH:L = 0x0008
CnVH:L = 0x0005
CNTH:L
...
channel (n) output
CHnF bit
TOF bit
Figure 19-16. CPWM signal with ELSnB:ELSnA = X:1
If (CnVH:L = 0x0000) or (CnVH:L is a negative value, that is, CnVH[7] = 1) then the
channel (n) output is a 0% duty cycle CPWM signal and CHnF bit is not set even when
there is the channel (n) match.
If (CnVH:L is a positive value, that is, CnVH[7] = 0), (CnVH:L ≥ MODH:L), and
(MODH:L ≠ 0x0000), then the channel (n) output is a 100% duty cycle CPWM signal
and CHnF bit is not set even when there is the channel (n) match. This implies that the
usable range of periods set by MODH:L is 0x0001 through 0x7FFE, or 0x7FFF if you do
not need to generate a 100% duty cycle CPWM signal. This is not a significant limitation
because the resulting period is much longer than required for normal applications.
The CPWM mode must not be used when the FTM counter is a free running counter.
19.5.8 Update of the registers with write buffers
This section describes the updating of registers that have write buffers.
19.5.8.1 MODH:L registers
If (CLKS[1:0] = 0:0), then MODH:L registers are updated when their second byte is
written.
If (CLKS[1:0] ≠ 0:0), then MODH:L registers are updated according to the CPWMS bit:
• If the selected mode is not CPWM mode, then MODH:L registers are updated after
both bytes have been written and the FTM counter changes from (MODH:L) to (all
zeroes). If the FTM counter is a free-running counter, then this update is made when
the FTM counter changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM mode, then MODH:L registers are updated after both
bytes have been written and the FTM counter changes from MODH:L to (MODH:L
– 0x0001).
338
counter
overflow
channel (n) match in
down counting
7
8
7
6
5
4
3
previous value
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
channel (n) match in
up counting
2
1
0
1
2
3
4
counter
overflow
channel (n) match in
down counting
5
6
7
8
7
6
5
NXP Semiconductors
...
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