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Memory map and register definition
14.7.1 Control Register (PMC_CTRL)
Address: 1850h base + 0h offset = 1850h
Bit
7
Read
GWREN
Write
Reset
0
POR
0
* Notes:
•
u = Unaffected by reset.
Field
7
General Write protection Enable
GWREN
General write protection enable by sharing with other trim write enable. This bit is the general write enable
control for the following registers:
• Temperature Offset Step Trim Register (PMC_TPTM)
• RC Oscillator Offset Step Trim Register (PMC_RC20KTRM)
• VREFH Configuration Register (PMC_VREFHCFG)
0
The general write protection is enabled.
1
The general write protection is disabled. Therefore, the related registers are writable.
6–3
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
2
VREFH Down
VREFDN
This bit controls whether to disable the VREFH regulator.
0
Enables the VREFH regulator.
1
Disables the VREFH regulator.
1
20 kHz RC oscillator Enable in Stop mode
RC20KENSTP
The default reset value is 1. In the Run mode this bit is always ON, and in the Stop mode it selects
whether to enable the 20 kHz RC oscillator.
0
Disables 20 kHz RC oscillator in the Stop mode.
1
Enables 20 kHz RC oscillator in the Stop mode.
0
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
222
6
5
0
0
0
0
0
PMC_CTRL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
VREFDN
0
0
u*
0
0
Description
2
1
RC20KENS
TP
u*
1
1
NXP Semiconductors
0
0
0
0
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